MC74ACT02DTR2G

@@ -0,0 +1,57 @@+# MC74ACT02DTR2G++**onsemi** · Logic Gates · TSSOP-14++MC74ACT02DTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1Y | output | Output of NOR gate 1. Push-pull CMOS output; drives HIGH when both 1A and 1B are LOW. IOH/IOL = -24 mA/+24 mA at VCC = 4.5 V. |+| 2 | 1A | input | Input A of NOR gate 1. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 3 | 1B | input | Input B of NOR gate 1. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 4 | 2Y | output | Output of NOR gate 2. Push-pull CMOS output; drives HIGH when both 2A and 2B are LOW. IOH/IOL = -24 mA/+24 mA at VCC = 4.5 V. |+| 5 | 2A | input | Input A of NOR gate 2. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 6 | 2B | input | Input B of NOR gate 2. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 7 | GND | power_in | Ground reference (0 V). All input/output voltages are referenced to this pin. Bypass VCC to GND with a local decoupling capacitor. |+| 8 | 3A | input | Input A of NOR gate 3. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 9 | 3B | input | Input B of NOR gate 3. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 10 | 3Y | output | Output of NOR gate 3. Push-pull CMOS output; drives HIGH when both 3A and 3B are LOW. IOH/IOL = -24 mA/+24 mA at VCC = 4.5 V. |+| 11 | 4A | input | Input A of NOR gate 4. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 12 | 4B | input | Input B of NOR gate 4. TTL-compatible input (VIH >= 2.0 V, VIL <= 0.8 V at VCC = 4.5-5.5 V). Input leakage +/-1.0 uA max. |+| 13 | 4Y | output | Output of NOR gate 4. Push-pull CMOS output; drives HIGH when both 4A and 4B are LOW. IOH/IOL = -24 mA/+24 mA at VCC = 4.5 V. |+| 14 | VCC | power_in | Positive supply input. ACT operating range 4.5-5.5 V (5.0 V typical). Absolute maximum 7.0 V. Quiescent ICC = 40 uA max at VCC = 5.5 V; bypass locally to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++Same part, different packaging or reel option.++- `MC74ACT02DTR2G`+- `MC74ACT02DTR2GDG`+- `MC74ACT02DTR2GDR2G`++## CAD (KiCad official)++- Symbol: `MC74ACT02DTR2G`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589838383956078592) (9 pp, sha256 `04b57f3cbb7d2b96`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mc74act02dtr2g-datasheet.pdf)

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