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Initial commit: component/mc14070bdr2g

Ray ·3c88369868 ·2mo ago
2 files changed +88
README.mdadded+54
@@ -0,0 +1,54 @@+# MC14070BDR2G++**onsemi** · Gates · SOIC-14++MC14070BDR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN1A | input | Gate A input 1. CMOS logic input to XOR gate A; VIL/VIH scale with VDD (e.g. at VDD=5V, VIL<=1.5V, VIH>=3.5V). Double-diode protected to VSS and VDD. |+| 2 | IN2A | input | Gate A input 2. CMOS logic input to XOR gate A; paired with IN1A. Double-diode input protection. |+| 3 | OUTA | output | Gate A buffered output. XOR of IN1A and IN2A. Sources/sinks TTL-compatible drive (e.g. IOL >= 0.51 mA at VDD=5V, VOL=0.4V). |+| 4 | OUTB | output | Gate B buffered output. XOR of IN1B and IN2B. CMOS full-rail output (VOH within 0.05V of VDD, VOL within 0.05V of VSS unloaded). |+| 5 | IN1B | input | Gate B input 1. CMOS logic input to XOR gate B. Unused inputs must be tied to VDD or VSS. |+| 6 | IN2B | input | Gate B input 2. CMOS logic input to XOR gate B; paired with IN1B. |+| 7 | VSS | power_in | Negative supply / ground reference. All input and output voltages are referenced to VSS. Typically tied to 0 V (0 to -18 V relative to VDD). |+| 8 | IN1C | input | Gate C input 1. CMOS logic input to XOR gate C. |+| 9 | IN2C | input | Gate C input 2. CMOS logic input to XOR gate C; paired with IN1C. |+| 10 | OUTC | output | Gate C buffered output. XOR of IN1C and IN2C. |+| 11 | OUTD | output | Gate D buffered output. XOR of IN1D and IN2D. |+| 12 | IN1D | input | Gate D input 1. CMOS logic input to XOR gate D. |+| 13 | IN2D | input | Gate D input 2. CMOS logic input to XOR gate D; paired with IN1D. |+| 14 | VDD | power_in | Positive supply. Operating range 3.0 to 18 Vdc (absolute max -0.5 to +18 V). Decouple locally to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | onsemi |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `MC14070BDR2G`+- `MC14070BDR2GDG`++## CAD (KiCad official)++- Symbol: `MC14070BDR2G`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [onsemi datasheet](docs/mc14070bdr2g-datasheet.pdf) (5 pp, sha256 `ff067a2348c14f92`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/mc14070bdr2g-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "mc14070bdr2g",+  "version": "0.1.0",+  "type": "component",+  "description": "onsemi Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "mc14070bdr2g"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "mc14070bdr2g.kicad_sym",+    "mc14070bdr2g.kicad_mod",+    "mc14070bdr2g.glb",+    "mc14070bdr2g.step",+    "mc14070bdr2g.lbr",+    "docs/hero.png",+    "docs/mc14070bdr2g-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file