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LTC2320IUKG-14#PBF
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Analog Devices Analog To Digital Converters (ADCs), QFN-52-EP(7x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+88@@ -0,0 +1,88 @@+# LTC2320IUKG-14#PBF++**Analog Devices** · Analog To Digital Converters (ADCs) · QFN-52-EP(7x8)++LTC2320IUKG-14#PBF from Analog Devices, in a QFN-52-EP(7x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AIN6- | input | Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND. |+| 2 | AIN6+ | input | Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND. |+| 3 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 4 | AIN5- | input | Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND. |+| 5 | AIN5+ | input | Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND. |+| 6 | REFOUT3 | output | Reference buffer 3 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded. |+| 7 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 8 | REF | output | Common 4.096V reference output; decouple to GND with 1µF low ESR ceramic capacitor; may be overdriven with single external reference for ADC cores 1-4. |+| 9 | REFOUT2 | output | Reference buffer 2 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded. |+| 10 | AIN4- | input | Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND. |+| 11 | AIN4+ | input | Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND. |+| 12 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 13 | AIN3- | input | Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND. |+| 14 | AIN3+ | input | Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND. |+| 15 | VDD | power_in | Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply. |+| 16 | AIN2- | input | Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND. |+| 17 | AIN2+ | input | Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND. |+| 18 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 19 | AIN1- | input | Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND. |+| 20 | AIN1+ | input | Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND. |+| 21 | VDD | power_in | Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply. |+| 22 | REFOUT1 | output | Reference buffer 1 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded. |+| 23 | SDR/DDR | input | Double data rate input; controls frequency of SCK and CLKOUT; tie to GND for SDR mode or to OVDD for DDR mode; CLKOUT is delayed version of SCK for both states. |+| 24 | CNV | input | Convert input; when high defines acquisition phase; when low initiates conversion and output data readout; must be driven at OVDD levels with low jitter pulse. |+| 25 | CMOS/LVDS | input | I/O mode select; ground for CMOS mode, tie to OVDD for LVDS mode, float for low power LVDS mode. |+| 26 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 27 | SDO1 | output | CMOS serial data output for ADC channel 1; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 28 | SDO2 | output | CMOS serial data output for ADC channel 2; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 29 | SDO3 | output | CMOS serial data output for ADC channel 3; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 30 | SDO4 | output | CMOS serial data output for ADC channel 4; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 31 | OVDD | power_in | I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor. |+| 32 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 33 | CLKOUT | output | Serial data clock output; provides skew-matched clock to latch SDO output at receiver; echoes SCK input with small delay; logic level determined by OVDD. |+| 34 | CLKOUTEN | input | CLKOUT enable control; tie to OVDD to disable CLKOUT for small power savings; ground this pin if CLKOUT is used. |+| 35 | SDO5 | output | CMOS serial data output for ADC channel 5; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 36 | SDO6 | output | CMOS serial data output for ADC channel 6; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 37 | OVDD | power_in | I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor. |+| 38 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 39 | SDO7 | output | CMOS serial data output for ADC channel 7; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 40 | SDO8 | output | CMOS serial data output for ADC channel 8; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data. |+| 41 | SCK | input | Serial data clock input; falling edge shifts conversion result MSB first in SDR mode; each edge in DDR mode; logic level determined by OVDD; 100MHz for SDR or 50MHz for DDR at 1.5Msps. |+| 42 | DNC | unconnected | Do not connect this pin in CMOS mode. |+| 43 | REFBUFEN | input | Reference buffer output enable; tie to VDD when using internal reference; tie to ground to disable internal REFOUT1-4 buffers for external references; has 500kΩ internal pull-up to VDD. |+| 44 | VDD | power_in | Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply. |+| 45 | REFOUT4 | output | Reference buffer 4 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded. |+| 46 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 47 | AIN8- | input | Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND. |+| 48 | AIN8+ | input | Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND. |+| 49 | GND | power_in | Ground; must be tied directly to a solid ground plane. |+| 50 | AIN7- | input | Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND. |+| 51 | AIN7+ | input | Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND. |+| 52 | VDD | power_in | Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply. |+| 53 | GND | power_in | Exposed pad ground; must be soldered to PCB ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | QFN-52-EP(7x8) |+| Category | ADC/DAC/Data Conversion |+| Pins | 53 |++## CAD (KiCad official)++- Symbol: `LTC2320IUKG-14#PBF`+- Footprint: `Package_DFN_QFN:QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm`+- 3D model: QFN-52-EP(7x8) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885897483849728) (34 pp, sha256 `321752c03d0fedaf`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ltc2320iukg-14-pbf-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "ltc2320iukg-14#pbf",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ltc2320iukg-14-pbf.kicad_sym",+ "ltc2320iukg-14-pbf.kicad_mod",+ "ltc2320iukg-14-pbf.glb",+ "ltc2320iukg-14-pbf.step",+ "ltc2320iukg-14-pbf.lbr",+ "docs/hero.png",+ "docs/ltc2320iukg-14-pbf-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "LTC2320IUKG-14#PBF",+ "manufacturer": "Analog Devices",+ "package": "QFN-52-EP(7x8)",+ "pin_count": 53,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Analog To Digital Converters (ADCs)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885897483849728",+ "parts": {+ "symbol": "ltc2320iukg-14-pbf.kicad_sym",+ "footprint": "ltc2320iukg-14-pbf.kicad_mod",+ "model_3d": "ltc2320iukg-14-pbf.glb",+ "model_3d_step": "ltc2320iukg-14-pbf.step",+ "lbr": "ltc2320iukg-14-pbf.lbr"+ },+ "distributor_links": {+ "lcsc": "C680019"+ },+ "pins": [+ {+ "number": "1",+ "name": "AIN6–",+ "type": "input",+ "description": "Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND."+ },+ {+ "number": "2",+ "name": "AIN6+",+ "type": "input",+ "description": "Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "4",+ "name": "AIN5–",+ "type": "input",+ "description": "Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND."+ },+ {+ "number": "5",+ "name": "AIN5+",+ "type": "input",+ "description": "Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND."+ },+ {+ "number": "6",+ "name": "REFOUT3",+ "type": "output",+ "description": "Reference buffer 3 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "8",+ "name": "REF",+ "type": "output",+ "description": "Common 4.096V reference output; decouple to GND with 1µF low ESR ceramic capacitor; may be overdriven with single external reference for ADC cores 1-4."+ },+ {+ "number": "9",+ "name": "REFOUT2",+ "type": "output",+ "description": "Reference buffer 2 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded."+ },+ {+ "number": "10",+ "name": "AIN4–",+ "type": "input",+ "description": "Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND."+ },+ {+ "number": "11",+ "name": "AIN4+",+ "type": "input",+ "description": "Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "13",+ "name": "AIN3–",+ "type": "input",+ "description": "Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND."+ },+ {+ "number": "14",+ "name": "AIN3+",+ "type": "input",+ "description": "Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND."+ },+ {+ "number": "15",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply."+ },+ {+ "number": "16",+ "name": "AIN2–",+ "type": "input",+ "description": "Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND."+ },+ {+ "number": "17",+ "name": "AIN2+",+ "type": "input",+ "description": "Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "19",+ "name": "AIN1–",+ "type": "input",+ "description": "Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND."+ },+ {+ "number": "20",+ "name": "AIN1+",+ "type": "input",+ "description": "Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND."+ },+ {+ "number": "21",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply."+ },+ {+ "number": "22",+ "name": "REFOUT1",+ "type": "output",+ "description": "Reference buffer 1 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded."+ },+ {+ "number": "23",+ "name": "SDR/DDR",+ "type": "input",+ "description": "Double data rate input; controls frequency of SCK and CLKOUT; tie to GND for SDR mode or to OVDD for DDR mode; CLKOUT is delayed version of SCK for both states."+ },+ {+ "number": "24",+ "name": "CNV",+ "type": "input",+ "description": "Convert input; when high defines acquisition phase; when low initiates conversion and output data readout; must be driven at OVDD levels with low jitter pulse."+ },+ {+ "number": "25",+ "name": "CMOS/LVDS",+ "type": "input",+ "description": "I/O mode select; ground for CMOS mode, tie to OVDD for LVDS mode, float for low power LVDS mode."+ },+ {+ "number": "26",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "27",+ "name": "SDO1",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 1; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "28",+ "name": "SDO2",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 2; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "29",+ "name": "SDO3",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 3; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "30",+ "name": "SDO4",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 4; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "31",+ "name": "OVDD",+ "type": "power_in",+ "description": "I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor."+ },+ {+ "number": "32",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "33",+ "name": "CLKOUT",+ "type": "output",+ "description": "Serial data clock output; provides skew-matched clock to latch SDO output at receiver; echoes SCK input with small delay; logic level determined by OVDD."+ },+ {+ "number": "34",+ "name": "CLKOUTEN",+ "type": "input",+ "description": "CLKOUT enable control; tie to OVDD to disable CLKOUT for small power savings; ground this pin if CLKOUT is used."+ },+ {+ "number": "35",+ "name": "SDO5",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 5; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "36",+ "name": "SDO6",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 6; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "37",+ "name": "OVDD",+ "type": "power_in",+ "description": "I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor."+ },+ {+ "number": "38",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "39",+ "name": "SDO7",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 7; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "40",+ "name": "SDO8",+ "type": "output",+ "description": "CMOS serial data output for ADC channel 8; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data."+ },+ {+ "number": "41",+ "name": "SCK",+ "type": "input",+ "description": "Serial data clock input; falling edge shifts conversion result MSB first in SDR mode; each edge in DDR mode; logic level determined by OVDD; 100MHz for SDR or 50MHz for DDR at 1.5Msps."+ },+ {+ "number": "42",+ "name": "DNC",+ "type": "unconnected",+ "description": "Do not connect this pin in CMOS mode."+ },+ {+ "number": "43",+ "name": "REFBUFEN",+ "type": "input",+ "description": "Reference buffer output enable; tie to VDD when using internal reference; tie to ground to disable internal REFOUT1-4 buffers for external references; has 500kΩ internal pull-up to VDD."+ },+ {+ "number": "44",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply."+ },+ {+ "number": "45",+ "name": "REFOUT4",+ "type": "output",+ "description": "Reference buffer 4 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded."+ },+ {+ "number": "46",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "47",+ "name": "AIN8–",+ "type": "input",+ "description": "Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND."+ },+ {+ "number": "48",+ "name": "AIN8+",+ "type": "input",+ "description": "Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND."+ },+ {+ "number": "49",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; must be tied directly to a solid ground plane."+ },+ {+ "number": "50",+ "name": "AIN7–",+ "type": "input",+ "description": "Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND."+ },+ {+ "number": "51",+ "name": "AIN7+",+ "type": "input",+ "description": "Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND."+ },+ {+ "number": "52",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply."+ },+ {+ "number": "53",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed pad ground; must be soldered to PCB ground plane."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 27–30, 33–34, 35–36, 39–42 have dual functionality: documented as CMOS mode (SDO1–8, CLKOUT, CL; Pin 34 (CLKOUTEN in CMOS mode) functions as CLKOUT– (differential output) in LVDS mode, changing fro; Pin 42 (DNC in CMOS mode) functions as SCK– (differential input) in LVDS mode, changing from unconne"+ ],+ "pages_sent": 34,+ "cost_usd": 0.8183,+ "at": "2026-09-17T17:13:12"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885897483849728",+ "pages": 34,+ "sha256": "321752c03d0fedaf",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 53,+ "described": 53,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}