LPC1758FBD80K

@@ -0,0 +1,121 @@+# LPC1758FBD80K++**NXP Semicon** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)++LPC1758FBD80K from NXP Semicon, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TDO/SWO | output | JTAG Test Data Out / Serial Wire trace output. |+| 2 | TDI | input | JTAG Test Data In. Internal pull-up. |+| 3 | TMS/SWDIO | bidirectional | JTAG Test Mode Select / Serial Wire Debug bidirectional data. |+| 4 | TRST | input | JTAG Test Reset input. Internal pull-up. |+| 5 | TCK/SWDCLK | input | JTAG Test Clock / Serial Wire Debug clock. |+| 6 | P0[26]/AD0[3]/AOUT/RXD3 | bidirectional | GPIO P0.26, muxed with ADC0 channel 3, 10-bit DAC output AOUT, and UART3 RXD. |+| 7 | P0[25]/AD0[2]/I2SRX_SDA/TXD3 | bidirectional | GPIO P0.25, muxed with ADC0 channel 2, I2S receive data, and UART3 TXD. |+| 8 | VDDA | power_in | Analog 3.3 V pad supply. Should be nominally VDD(3V3) but isolated for noise; powers ADC/DAC. |+| 9 | VSSA | power_in | Analog ground; 0 V reference for the analog block, isolated from VSS. |+| 10 | VREFP | power_in | ADC/DAC positive reference voltage; nominally VDDA. |+| 11 | RSTOUT | output | 3.3 V reset-out indicator; LOW while the MCU is in reset. |+| 12 | VREFN | power_in | ADC/DAC negative reference voltage; nominally VSS. |+| 13 | RTCX1 | input | Input to the 32.768 kHz RTC oscillator circuit. |+| 14 | RESET | input | Active-low external reset input; TTL hysteresis, 5 V tolerant; 50 ns min pulse. |+| 15 | RTCX2 | output | Output from the RTC oscillator amplifier. |+| 16 | VBAT | power_in | RTC battery/back-up supply; 3.3 V powers the RTC domain when VDD is removed. |+| 17 | P1[31]/SCK1/AD0[5] | bidirectional | GPIO P1.31, muxed with SSP1 SCK and ADC0 channel 5. |+| 18 | P1[30]/VBUS/AD0[4] | bidirectional | GPIO P1.30, muxed with USB VBUS sense input and ADC0 channel 4. VBUS must be HIGH for USB reset. |+| 19 | XTAL1 | input | Main oscillator input / external clock input. |+| 20 | XTAL2 | output | Main oscillator amplifier output. |+| 21 | VDD(3V3) | power_in | 3.3 V I/O supply voltage (one of four VDD(3V3) pins). |+| 22 | P0[29]/USB_D+ | bidirectional | GPIO P0.29 / USB bidirectional D+ line. |+| 23 | P0[30]/USB_D- | bidirectional | GPIO P0.30 / USB bidirectional D- line. |+| 24 | VSS | power_in | Digital ground; 0 V reference (one of six VSS pins). |+| 25 | P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] | bidirectional | GPIO P1.18, muxed with USB GoodLink LED output, PWM1 ch1, and Timer1 capture 0. |+| 26 | P1[19]/MCOA0/USB_PPWR/CAP1[1] | bidirectional | GPIO P1.19, muxed with motor-control PWM channel 0 A output, USB port-power enable, and Timer1 capture 1. |+| 27 | P1[20]/MCI0/PWM1[2]/SCK0 | bidirectional | GPIO P1.20, muxed with MC PWM ch0 input / QEI PHA, PWM1 ch2, and SSP0 SCK. |+| 28 | P1[22]/MCOB0/USB_PWRD/MAT1[0] | bidirectional | GPIO P1.22, muxed with MC PWM ch0 B output, USB power-status input, and Timer1 match 0. |+| 29 | P1[23]/MCI1/PWM1[4]/MISO0 | bidirectional | GPIO P1.23, muxed with MC PWM ch1 input / QEI PHB, PWM1 ch4, and SSP0 MISO. |+| 30 | P1[24]/MCI2/PWM1[5]/MOSI0 | bidirectional | GPIO P1.24, muxed with MC PWM ch2 input / QEI INDEX, PWM1 ch5, and SSP0 MOSI. |+| 31 | P1[25]/MCOA1/MAT1[1] | bidirectional | GPIO P1.25, muxed with MC PWM ch1 A output and Timer1 match 1. |+| 32 | P1[26]/MCOB1/PWM1[6]/CAP0[0] | bidirectional | GPIO P1.26, muxed with MC PWM ch1 B output, PWM1 ch6, and Timer0 capture 0. |+| 33 | VSS | power_in | Digital ground; 0 V reference. |+| 34 | VDD(REG)(3V3) | power_in | 3.3 V supply for the on-chip core voltage regulator only. |+| 35 | P1[28]/MCOA2/PCAP1[0]/MAT0[0] | bidirectional | GPIO P1.28, muxed with MC PWM ch2 A output, PWM1 capture 0, and Timer0 match 0. |+| 36 | P1[29]/MCOB2/PCAP1[1]/MAT0[1] | bidirectional | GPIO P1.29, muxed with MC PWM ch2 B output, PWM1 capture 1, and Timer0 match 1. |+| 37 | P0[0]/RD1/TXD3/SDA1 | bidirectional | GPIO P0.0, muxed with CAN1 RD, UART3 TXD, and I2C1 SDA (not open-drain). |+| 38 | P0[1]/TD1/RXD3/SCL1 | bidirectional | GPIO P0.1, muxed with CAN1 TD, UART3 RXD, and I2C1 SCL (not open-drain). |+| 39 | P0[10]/TXD2/SDA2/MAT3[0] | bidirectional | GPIO P0.10, muxed with UART2 TXD, I2C2 SDA (not open-drain), and Timer3 match 0. |+| 40 | P0[11]/RXD2/SCL2/MAT3[1] | bidirectional | GPIO P0.11, muxed with UART2 RXD, I2C2 SCL (not open-drain), and Timer3 match 1. |+| 41 | P2[10]/EINT0/NMI | bidirectional | GPIO P2.10, muxed with external interrupt 0 and NMI. LOW during reset invokes the ISP command handler. |+| 42 | VDD(3V3) | power_in | 3.3 V I/O supply voltage. |+| 43 | VSS | power_in | Digital ground; 0 V reference. |+| 44 | P0[22]/RTS1/TD1 | bidirectional | GPIO P0.22, muxed with UART1 RTS (also RS-485 output-enable) and CAN1 TD. |+| 45 | P0[18]/DCD1/MOSI0/MOSI | bidirectional | GPIO P0.18, muxed with UART1 DCD, SSP0 MOSI, and SPI MOSI. |+| 46 | P0[17]/CTS1/MISO0/MISO | bidirectional | GPIO P0.17, muxed with UART1 CTS, SSP0 MISO, and SPI MISO. |+| 47 | P0[15]/TXD1/SCK0/SCK | bidirectional | GPIO P0.15, muxed with UART1 TXD, SSP0 SCK, and SPI SCK. |+| 48 | P0[16]/RXD1/SSEL0/SSEL | bidirectional | GPIO P0.16, muxed with UART1 RXD, SSP0 SSEL, and SPI SSEL. |+| 49 | P2[9]/USB_CONNECT/RXD2 | bidirectional | GPIO P2.9, muxed with USB SoftConnect control output and UART2 RXD. |+| 50 | P2[8]/TD2/TXD2 | bidirectional | GPIO P2.8, muxed with CAN2 TD and UART2 TXD. |+| 51 | P2[7]/RD2/RTS1 | bidirectional | GPIO P2.7, muxed with CAN2 RD and UART1 RTS. |+| 52 | P2[6]/PCAP1[0]/RI1/TRACECLK | bidirectional | GPIO P2.6, muxed with PWM1 capture 0, UART1 RI, and trace clock output. |+| 53 | P2[5]/PWM1[6]/DTR1/TRACEDATA[0] | bidirectional | GPIO P2.5, muxed with PWM1 ch6, UART1 DTR (also RS-485 OE), and trace data bit 0. |+| 54 | P2[4]/PWM1[5]/DSR1/TRACEDATA[1] | bidirectional | GPIO P2.4, muxed with PWM1 ch5, UART1 DSR, and trace data bit 1. |+| 55 | P2[3]/PWM1[4]/DCD1/TRACEDATA[2] | bidirectional | GPIO P2.3, muxed with PWM1 ch4, UART1 DCD, and trace data bit 2. |+| 56 | VDD(3V3) | power_in | 3.3 V I/O supply voltage. |+| 57 | VSS | power_in | Digital ground; 0 V reference. |+| 58 | P2[2]/PWM1[3]/CTS1/TRACEDATA[3] | bidirectional | GPIO P2.2, muxed with PWM1 ch3, UART1 CTS, and trace data bit 3. |+| 59 | P2[1]/PWM1[2]/RXD1 | bidirectional | GPIO P2.1, muxed with PWM1 ch2 and UART1 RXD. |+| 60 | P2[0]/PWM1[1]/TXD1 | bidirectional | GPIO P2.0, muxed with PWM1 ch1 and UART1 TXD. |+| 61 | P0[9]/I2STX_SDA/MOSI1/MAT2[3] | bidirectional | GPIO P0.9, muxed with I2S TX data (SD), SSP1 MOSI, and Timer2 match 3. |+| 62 | P0[8]/I2STX_WS/MISO1/MAT2[2] | bidirectional | GPIO P0.8, muxed with I2S TX word-select, SSP1 MISO, and Timer2 match 2. |+| 63 | P0[7]/I2STX_CLK/SCK1/MAT2[1] | bidirectional | GPIO P0.7, muxed with I2S TX clock (SCK), SSP1 SCK, and Timer2 match 1. |+| 64 | P0[6]/I2SRX_SDA/SSEL1/MAT2[0] | bidirectional | GPIO P0.6, muxed with I2S RX data, SSP1 SSEL, and Timer2 match 0. |+| 65 | P4[28]/RX_MCLK/MAT2[0]/TXD3 | bidirectional | GPIO P4.28, muxed with I2S receive master clock, Timer2 match 0, and UART3 TXD. |+| 66 | VSS | power_in | Digital ground; 0 V reference. |+| 67 | VDD(REG)(3V3) | power_in | 3.3 V supply for the on-chip core voltage regulator only. |+| 68 | P4[29]/TX_MCLK/MAT2[1]/RXD3 | bidirectional | GPIO P4.29, muxed with I2S transmit master clock, Timer2 match 1, and UART3 RXD. |+| 69 | P1[15]/ENET_REF_CLK | bidirectional | GPIO P1.15 / Ethernet RMII reference clock (LPC1758 only). |+| 70 | P1[14]/ENET_RX_ER | bidirectional | GPIO P1.14 / Ethernet receive error (LPC1758 only). |+| 71 | P1[10]/ENET_RXD1 | bidirectional | GPIO P1.10 / Ethernet RMII receive data 1 (LPC1758 only). |+| 72 | P1[9]/ENET_RXD0 | bidirectional | GPIO P1.9 / Ethernet RMII receive data 0 (LPC1758 only). |+| 73 | P1[8]/ENET_CRS | bidirectional | GPIO P1.8 / Ethernet carrier sense (LPC1758 only). |+| 74 | P1[4]/ENET_TX_EN | bidirectional | GPIO P1.4 / Ethernet transmit-enable (LPC1758 only). |+| 75 | P1[1]/ENET_TXD1 | bidirectional | GPIO P1.1 / Ethernet RMII transmit data 1 (LPC1758 only). |+| 76 | P1[0]/ENET_TXD0 | bidirectional | GPIO P1.0 / Ethernet RMII transmit data 0 (LPC1758 only). |+| 77 | VDD(3V3) | power_in | 3.3 V I/O supply voltage. |+| 78 | VSS | power_in | Digital ground; 0 V reference. |+| 79 | P0[2]/TXD0/AD0[7] | bidirectional | GPIO P0.2, muxed with UART0 TXD and ADC0 channel 7. |+| 80 | P0[3]/RXD0/AD0[6] | bidirectional | GPIO P0.3, muxed with UART0 RXD and ADC0 channel 6. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | NXP Semicon |+| Package | LQFP-80(12x12) |+| Category | MCU |+| Pins | 80 |++## Ordering variants++Same part, different packaging or reel option.++- `LPC1758FBD80K`++## CAD (KiCad official)++- Symbol: `LPC1758FBD80K`+- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`+- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [NXP Semicon datasheet](https://www.nxp.com/docs/en/data-sheet/LPC1758FBD80K.pdf) (80 pp, sha256 `3db9019ee5b7e77d`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lpc1758fbd80k-datasheet.pdf)