component
LP2950CDT-3.3RKG
Public Made by Adomby adom
onsemi LP2950CDT 3 3RKG Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-252-2(DPAK). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C233210). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+25−5
lp2950cdt-3-3rkg.lbr+20−2@@ -57,6 +57,18 @@ <smd name="1" x="-5.0400" y="2.2800" dx="2.2000" dy="1.2000" layer="1"/> <smd name="2" x="1.2600" y="-0.0000" dx="6.4000" dy="5.8000" layer="1"/> <smd name="3" x="-5.0400" y="-2.2800" dx="2.2000" dy="1.2000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-5.0400" y="3.1400"/>+ <vertex x="-5.3800" y="3.6100"/>+ <vertex x="-4.7000" y="3.6100"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="3.1100" y="3.2500"/>+ <vertex x="3.1100" y="-3.2500"/>+ <vertex x="-3.1100" y="-3.2500"/>+ <vertex x="-3.1100" y="2.2500"/>+ <vertex x="-2.1100" y="3.2500"/>+ </polygon> <wire x1="-3.3100" y1="3.4500" x2="-3.3100" y2="3.1800" width="0.1200" layer="21"/> <wire x1="-3.3100" y1="-3.4500" x2="-3.3100" y2="-3.1800" width="0.1200" layer="21"/> <wire x1="3.1100" y1="3.4500" x2="-3.3100" y2="3.4500" width="0.1200" layer="21"/>@@ -72,7 +84,7 @@ <wire x1="4.1100" y1="-2.7000" x2="3.1100" y2="-2.7000" width="0.1000" layer="51"/> <text x="0" y="4.050" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-4.050" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-5.0400" y="3.1400"/><vertex x="-5.3800" y="3.6100"/><vertex x="-4.7000" y="3.6100"/></polygon></package>+</package> </packages> <symbols> <symbol name="LP2950CDT-3.3RKG">@@ -102,7 +114,13 @@ <connect gate="G$1" pin="Tab/GND" pad="2"/> <connect gate="G$1" pin="Output" pad="3"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="LP2950CDT-3.3RKG" constant="no"/>+ <attribute name="MANUFACTURER" value="onsemi LP2950CDT 3 3RKG" constant="no"/>+ <attribute name="LCSC_PN" value="C233210" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+5−3@@ -26,7 +26,9 @@ "model_3d_step": "lp2950cdt-3-3rkg.step", "lbr": "lp2950cdt-3-3rkg.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C233210"+ }, "pins": [ { "number": "1",@@ -44,13 +46,13 @@ "number": "3", "name": "Output", "type": "power_out",- "description": "Regulated 3.3 V output, up to 100 mA continuous (typ. current limit 220 mA). Requires ≥1.0 µF output capacitor for loop stability."+ "description": "Regulated 3.3 V output, up to 100 mA continuous (typ. current limit 220 mA). Requires \u22651.0 \u00b5F output capacitor for loop stability." }, { "number": "4", "name": "Tab/GND", "type": "power_in",- "description": "DPAK exposed metal heatsink tab. Internally bonded to Pin 2 (Ground). Solder to a copper pour to lower junction-to-ambient thermal resistance (RθJA = 92 °C/W with recommended pad, RθJC = 6.0 °C/W)."+ "description": "DPAK exposed metal heatsink tab. Internally bonded to Pin 2 (Ground). Solder to a copper pour to lower junction-to-ambient thermal resistance (R\u03b8JA = 92 \u00b0C/W with recommended pad, R\u03b8JC = 6.0 \u00b0C/W)." } ], "provenance": {