component
LMX2572LPRHAT
Public Made by Adomby adom
Texas Instruments Clock Generators / Frequency Synthesizers / PLL, HVQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# LMX2572LPRHAT++**Texas Instruments** · Clock Generators / Frequency Synthesizers / PLL · HVQFN-40-EP(6x6)++LMX2572LPRHAT from Texas Instruments, in a HVQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CE | input | Chip enable: high-impedance CMOS input for 1.8-V to 3.3-V logic; active HIGH powers on the device. |+| 2 | GND | power_in | VCO ground. |+| 3 | VbiasVCO | passive | Bypass VCO bias; connect a 470-nF (X7R) decoupling capacitor to VCO ground as close to this pin as possible. |+| 4 | GND | power_in | VCO ground. |+| 5 | SYNC | input | Phase synchronization trigger; configurable to accept CMOS input (1.8-V to 3.3-V logic) or differential input. |+| 6 | GND | power_in | Digital ground. |+| 7 | VccDIG | power_in | Digital power supply; connect a 0.1-µF decoupling capacitor to digital ground. |+| 8 | OSCinP | input | Reference input clock (+); high-impedance self-biasing pin that requires AC-coupling. |+| 9 | OSCinM | input | Reference input clock (-); high-impedance self-biasing pin that requires AC-coupling. |+| 10 | VregIN | passive | Input reference path regulator output; connect a 1-µF decoupling capacitor to RF ground as close to this pin as possible. |+| 11 | VccCP | power_in | Supply for charge pump; connect a 0.1-µF decoupling capacitor to charge pump ground. |+| 12 | CPout | output | Charge pump output; place C1 of the loop filter close to this pin. |+| 13 | GND | power_in | Charge pump ground. |+| 14 | GND | power_in | Digital ground. |+| 15 | VccMASH | power_in | Digital power supply; connect a 1-µF decoupling capacitor to digital ground. |+| 16 | SCK | input | SPI clock: high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 17 | SDI | input | SPI data: high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 18 | RFoutBM | output | Differential output B (-): low-impedance output that requires AC-coupling. |+| 19 | RFoutBP | output | Differential output B (+): low-impedance output that requires AC-coupling. |+| 20 | MUXout | output | Multiplexed output configurable between lock detect and register readback. |+| 21 | VccBUF | power_in | Supply for output buffers; connect a 0.1-µF decoupling capacitor to RF ground. |+| 22 | RFoutAM | output | Differential output A (-): low-impedance output that requires AC-coupling. |+| 23 | RFoutAP | output | Differential output A (+): low-impedance output that requires AC-coupling. |+| 24 | CSB | input | SPI latch: high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 25 | GND | power_in | VCO ground. |+| 26 | VccVCO2 | power_in | Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground. |+| 27 | VbiasVCO2 | passive | Bypass VCO bias; connect a 100-nF (X7R) decoupling capacitor to VCO ground. |+| 28 | SysRefReq | input | FSK I2S frame sync input: high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 29 | VrefVCO2 | passive | Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground. |+| 30 | RampClk | input | Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode; can also serve as FSK I2S clock input; high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 31 | GND | power_in | VCO ground. |+| 32 | RampDir | input | Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping mode; can also serve as FSK I2S data input; high-impedance CMOS input for 1.8-V to 3.3-V logic. |+| 33 | VbiasVARAC | passive | Bypass VCO varactor bias; connect a 10-µF decoupling capacitor to VCO ground. |+| 34 | GND | power_in | VCO ground. |+| 35 | Vtune | input | VCO tuning voltage input; connect a 1.5-nF or larger capacitor to VCO ground (see External Loop Filter). |+| 36 | VrefVCO | passive | Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground. |+| 37 | VccVCO | power_in | Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground. |+| 38 | VregVCO | passive | Bypass VCO regulator node; connect a 10-nF decoupling capacitor to VCO ground. |+| 39 | GND | power_in | VCO ground. |+| 40 | GND | power_in | Digital ground. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HVQFN-40-EP(6x6) |+| Category | RTC/Clock Chip |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `LMX2572LPRHAT`+- Footprint: `Package_DFN_QFN:HVQFN-40-1EP_6x6mm_P0.5mm_EP4.1x4.1mm`+- 3D model: HVQFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `lmx2572lprhat-etched.step` / `lmx2572lprhat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmx2572lprhat.step` / `lmx2572lprhat.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmx2572lp) (87 pp, sha256 `69f0bb4362d891e6`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmx2572lprhat-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rtc-clock chip",+ "lmx2572lprhat",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmx2572lprhat.kicad_sym",+ "lmx2572lprhat.kicad_mod",+ "lmx2572lprhat.glb",+ "lmx2572lprhat.step",+ "lmx2572lprhat.lbr",+ "docs/hero.png",+ "docs/lmx2572lprhat-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmx2572lprhat-hero.glb",+ "lmx2572lprhat-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMX2572LPRHAT",+ "manufacturer": "Texas Instruments",+ "package": "HVQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "RTC/Clock Chip",+ "subcategory": "Clock Generators / Frequency Synthesizers / PLL",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmx2572lp",+ "parts": {+ "symbol": "lmx2572lprhat.kicad_sym",+ "footprint": "lmx2572lprhat.kicad_mod",+ "model_3d": "lmx2572lprhat-hero.glb",+ "model_3d_plain": "lmx2572lprhat.glb",+ "model_3d_step": "lmx2572lprhat-etched.step",+ "model_3d_step_plain": "lmx2572lprhat.step",+ "lbr": "lmx2572lprhat.lbr"+ },+ "distributor_links": {+ "lcsc": "C2662636",+ "digikey": "296-51375-2-ND",+ "mouser": "595-LMX2572LPRHAT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:06:49Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-51375-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-LMX2572LPRHAT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CE",+ "type": "input",+ "description": "Chip enable: high-impedance CMOS input for 1.8-V to 3.3-V logic; active HIGH powers on the device."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "3",+ "name": "VbiasVCO",+ "type": "passive",+ "description": "Bypass VCO bias; connect a 470-nF (X7R) decoupling capacitor to VCO ground as close to this pin as possible."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "5",+ "name": "SYNC",+ "type": "input",+ "description": "Phase synchronization trigger; configurable to accept CMOS input (1.8-V to 3.3-V logic) or differential input."+ },+ {+ "number": "6",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "7",+ "name": "VccDIG",+ "type": "power_in",+ "description": "Digital power supply; connect a 0.1-µF decoupling capacitor to digital ground."+ },+ {+ "number": "8",+ "name": "OSCinP",+ "type": "input",+ "description": "Reference input clock (+); high-impedance self-biasing pin that requires AC-coupling."+ },+ {+ "number": "9",+ "name": "OSCinM",+ "type": "input",+ "description": "Reference input clock (-); high-impedance self-biasing pin that requires AC-coupling."+ },+ {+ "number": "10",+ "name": "VregIN",+ "type": "passive",+ "description": "Input reference path regulator output; connect a 1-µF decoupling capacitor to RF ground as close to this pin as possible."+ },+ {+ "number": "11",+ "name": "VccCP",+ "type": "power_in",+ "description": "Supply for charge pump; connect a 0.1-µF decoupling capacitor to charge pump ground."+ },+ {+ "number": "12",+ "name": "CPout",+ "type": "output",+ "description": "Charge pump output; place C1 of the loop filter close to this pin."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Charge pump ground."+ },+ {+ "number": "14",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "15",+ "name": "VccMASH",+ "type": "power_in",+ "description": "Digital power supply; connect a 1-µF decoupling capacitor to digital ground."+ },+ {+ "number": "16",+ "name": "SCK",+ "type": "input",+ "description": "SPI clock: high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "17",+ "name": "SDI",+ "type": "input",+ "description": "SPI data: high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "18",+ "name": "RFoutBM",+ "type": "output",+ "description": "Differential output B (-): low-impedance output that requires AC-coupling."+ },+ {+ "number": "19",+ "name": "RFoutBP",+ "type": "output",+ "description": "Differential output B (+): low-impedance output that requires AC-coupling."+ },+ {+ "number": "20",+ "name": "MUXout",+ "type": "output",+ "description": "Multiplexed output configurable between lock detect and register readback."+ },+ {+ "number": "21",+ "name": "VccBUF",+ "type": "power_in",+ "description": "Supply for output buffers; connect a 0.1-µF decoupling capacitor to RF ground."+ },+ {+ "number": "22",+ "name": "RFoutAM",+ "type": "output",+ "description": "Differential output A (-): low-impedance output that requires AC-coupling."+ },+ {+ "number": "23",+ "name": "RFoutAP",+ "type": "output",+ "description": "Differential output A (+): low-impedance output that requires AC-coupling."+ },+ {+ "number": "24",+ "name": "CSB",+ "type": "input",+ "description": "SPI latch: high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "26",+ "name": "VccVCO2",+ "type": "power_in",+ "description": "Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground."+ },+ {+ "number": "27",+ "name": "VbiasVCO2",+ "type": "passive",+ "description": "Bypass VCO bias; connect a 100-nF (X7R) decoupling capacitor to VCO ground."+ },+ {+ "number": "28",+ "name": "SysRefReq",+ "type": "input",+ "description": "FSK I2S frame sync input: high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "29",+ "name": "VrefVCO2",+ "type": "passive",+ "description": "Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground."+ },+ {+ "number": "30",+ "name": "RampClk",+ "type": "input",+ "description": "Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode; can also serve as FSK I2S clock input; high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "31",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "32",+ "name": "RampDir",+ "type": "input",+ "description": "Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping mode; can also serve as FSK I2S data input; high-impedance CMOS input for 1.8-V to 3.3-V logic."+ },+ {+ "number": "33",+ "name": "VbiasVARAC",+ "type": "passive",+ "description": "Bypass VCO varactor bias; connect a 10-µF decoupling capacitor to VCO ground."+ },+ {+ "number": "34",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "35",+ "name": "Vtune",+ "type": "input",+ "description": "VCO tuning voltage input; connect a 1.5-nF or larger capacitor to VCO ground (see External Loop Filter)."+ },+ {+ "number": "36",+ "name": "VrefVCO",+ "type": "passive",+ "description": "Bypass VCO supply reference; connect a 10-µF decoupling capacitor to VCO ground."+ },+ {+ "number": "37",+ "name": "VccVCO",+ "type": "power_in",+ "description": "Supply for VCO; connect a 1-µF decoupling capacitor to VCO ground."+ },+ {+ "number": "38",+ "name": "VregVCO",+ "type": "passive",+ "description": "Bypass VCO regulator node; connect a 10-nF decoupling capacitor to VCO ground."+ },+ {+ "number": "39",+ "name": "GND",+ "type": "power_in",+ "description": "VCO ground."+ },+ {+ "number": "40",+ "name": "GND",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package name mismatch: the requested hint is HVQFN-40-EP(6x6), while the datasheet and ordering adde; The exposed die pad (DAP) has no printed pin number in the datasheet (listed as '—'). It is included; Pin types for bypass/decoupling and regulator-node pins (VbiasVCO, VbiasVCO2, VbiasVARAC, VrefVCO, V",+ "exposed pad 41 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.1036,+ "at": "2026-10-08T20:05:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmx2572lp",+ "pages": 87,+ "sha256": "69f0bb4362d891e6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmx2572lprhat.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fd098c9be49cbb87441f4e4e025c27ec4faf99e55b57717c22b6e489282c72c2",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmx2572lprhat-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7dbdd7b8394f3006118cf265792afa26a64bf3b203df714caedb35a370a5f0d2",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}