component
LMR16020PDDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN 296-47335-2-ND, LCSC_PN C190006). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+24−8
lmr16020pddar.lbr+17−4@@ -66,6 +66,12 @@ <smd name="9@2" x="-0.6025" y="-0.7750" dx="1.2050" dy="1.5500" layer="1"/> <smd name="9@3" x="0.6025" y="0.7750" dx="1.2050" dy="1.5500" layer="1"/> <smd name="9@4" x="0.6025" y="-0.7750" dx="1.2050" dy="1.5500" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.5000" y="2.5000"/>+ <vertex x="-2.7400" y="2.8300"/>+ <vertex x="-2.2600" y="2.8300"/>+ <vertex x="-2.5000" y="2.5000"/>+ </polygon> <wire x1="-2.0750" y1="2.5750" x2="2.0750" y2="2.5750" width="0.1500" layer="21"/> <wire x1="-2.0750" y1="-2.5750" x2="2.0750" y2="-2.5750" width="0.1500" layer="21"/> <wire x1="-1.9500" y1="1.4500" x2="-0.9500" y2="2.4500" width="0.1500" layer="51"/>@@ -75,7 +81,7 @@ <wire x1="1.9500" y1="-2.4500" x2="-1.9500" y2="-2.4500" width="0.1500" layer="51"/> <text x="0" y="3.460" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-3.460" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.5000" y="2.5000"/><vertex x="-2.7400" y="2.8300"/><vertex x="-2.2600" y="2.8300"/><vertex x="-2.5000" y="2.5000"/></polygon></package>+</package> </packages> <symbols> <symbol name="LMR16020PDDAR">@@ -90,7 +96,7 @@ <pin name="EN" x="-17.78" y="0" length="middle" direction="in"/> <pin name="RT/SYNC" x="-17.78" y="-2.54" length="middle" direction="io"/> <pin name="FB" x="-17.78" y="-5.08" length="middle" direction="in"/>- <pin name="Thermal Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="Thermal_Pad" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/> <pin name="SW" x="17.78" y="0" length="middle" direction="out" rot="R180"/> <pin name="GND" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/> <pin name="PGOOD" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>@@ -110,12 +116,19 @@ <connect gate="G$1" pin="EN" pad="3"/> <connect gate="G$1" pin="RT/SYNC" pad="4"/> <connect gate="G$1" pin="FB" pad="5"/>- <connect gate="G$1" pin="Thermal Pad" pad="9 9@2 9@3 9@4"/>+ <connect gate="G$1" pin="Thermal_Pad" pad="9 9@2 9@3 9@4"/> <connect gate="G$1" pin="SW" pad="8"/> <connect gate="G$1" pin="GND" pad="7"/> <connect gate="G$1" pin="PGOOD" pad="6"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="LMR16020PDDAR" constant="no"/>+ <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+ <attribute name="DIGIKEY_PN" value="296-47335-2-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C190006" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+7−4@@ -26,13 +26,16 @@ "model_3d_step": "lmr16020pddar.step", "lbr": "lmr16020pddar.lbr" },- "distributor_links": {},+ "distributor_links": {+ "digikey": "296-47335-2-ND",+ "lcsc": "C190006"+ }, "pins": [ { "number": "1", "name": "BOOT", "type": "passive",- "description": "Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1 µF capacitor from BOOT to SW. Absolute max BOOT-to-GND = 71 V; BOOT-to-SW = 6.5 V."+ "description": "Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1 \u00b5F capacitor from BOOT to SW. Absolute max BOOT-to-GND = 71 V; BOOT-to-SW = 6.5 V." }, { "number": "2",@@ -62,7 +65,7 @@ "number": "6", "name": "PGOOD", "type": "output",- "description": "Power-Good open-drain output flag. Use a 10 kΩ to 100 kΩ pull-up resistor to a logic rail or DC voltage no higher than 7 V. Asserts when FB is within roughly 94%-107% of the reference."+ "description": "Power-Good open-drain output flag. Use a 10 k\u03a9 to 100 k\u03a9 pull-up resistor to a logic rail or DC voltage no higher than 7 V. Asserts when FB is within roughly 94%-107% of the reference." }, { "number": "7",@@ -74,7 +77,7 @@ "number": "8", "name": "SW", "type": "power_out",- "description": "Switching output of the regulator, internally connected to the high-side power MOSFET (155 mΩ RDS(on)). Connect to the power inductor and to the catch diode's cathode. SW-to-GND rating: -3 V to 65 V absolute max."+ "description": "Switching output of the regulator, internally connected to the high-side power MOSFET (155 m\u03a9 RDS(on)). Connect to the power inductor and to the catch diode's cathode. SW-to-GND rating: -3 V to 65 V absolute max." }, { "number": "9",