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LMK04808BISQX
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+101@@ -0,0 +1,101 @@+# LMK04808BISQX++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · WQFN-64-EP(9x9)++LMK04808BISQX from Texas Instruments, in a WQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLKout0 | output | Programmable clock output 0 (clock group 0). |+| 2 | CLKout0* | output | Programmable clock output 0 complement (clock group 0). |+| 3 | CLKout1* | output | Programmable clock output 1 complement (clock group 0). |+| 4 | CLKout1 | output | Programmable clock output 1 (clock group 0). |+| 5 | NC | unconnected | No connection; must be left floating. |+| 6 | SYNC | bidirectional | Programmable clock output synchronization input or programmable status pin. |+| 7 | NC | unconnected | No connection; must be left floating. |+| 8 | NC | unconnected | No connection; must be left floating. |+| 9 | NC | unconnected | No connection; must be left floating. |+| 10 | Vcc1 | power_in | Power supply for VCO LDO regulator. |+| 11 | LDObyp1 | passive | LDO bypass pin; bypass to ground with 10 µF capacitor. |+| 12 | LDObyp2 | passive | LDO bypass pin; bypass to ground with 0.1 µF capacitor. |+| 13 | CLKout2 | output | Programmable clock output 2 (clock group 1). |+| 14 | CLKout2* | output | Programmable clock output 2 complement (clock group 1). |+| 15 | CLKout3* | output | Programmable clock output 3 complement (clock group 1). |+| 16 | CLKout3 | output | Programmable clock output 3 (clock group 1). |+| 17 | Vcc2 | power_in | Power supply for clock group 1 outputs (CLKout2 and CLKout3). |+| 18 | Vcc3 | power_in | Power supply for clock group 2 outputs (CLKout4 and CLKout5). |+| 19 | CLKout4 | output | Programmable clock output 4 (clock group 2). |+| 20 | CLKout4* | output | Programmable clock output 4 complement (clock group 2). |+| 21 | CLKout5* | output | Programmable clock output 5 complement (clock group 2). |+| 22 | CLKout5 | output | Programmable clock output 5 (clock group 2). |+| 23 | GND | power_in | Ground connection. |+| 24 | Vcc4 | power_in | Power supply for digital circuitry. |+| 25 | FBCLKin/Fin/CLKin1 | input | Reference clock input port 1 for PLL1 (AC or DC coupled); functions as feedback input in 0-delay mode or external VCO input. |+| 26 | FBCLKin*/Fin*/CLKin1* | input | Reference clock input port 1 complement for PLL1 (AC or DC coupled). |+| 27 | Status_Holdover | bidirectional | Programmable status pin; default readback output, programmable as holdover mode indicator. |+| 28 | CLKin0 | input | Reference clock input port 0 for PLL1 (AC or DC coupled). |+| 29 | CLKin0* | input | Reference clock input port 0 complement for PLL1 (AC or DC coupled). |+| 30 | Vcc5 | power_in | Power supply for clock inputs and OSCout1 output. |+| 31 | OSCout1 | output | LVPECL buffered output 1 from oscillator input port. |+| 32 | OSCout1* | output | LVPECL buffered output 1 complement from oscillator input port. |+| 33 | Status_LD | bidirectional | Programmable status pin; default lock detect for PLL1 and PLL2. |+| 34 | CPout1 | output | Charge pump 1 output for PLL1 loop filter. |+| 35 | Vcc6 | power_in | Power supply for PLL1 and charge pump 1. |+| 36 | OSCin | input | Oscillator input for feedback to PLL1 and reference to PLL2 (AC coupled). |+| 37 | OSCin* | input | Oscillator input complement for feedback to PLL1 and reference to PLL2 (AC coupled). |+| 38 | Vcc7 | power_in | Power supply for oscillator input, OSCout0 output, and PLL2 circuitry. |+| 39 | OSCout0 | output | Programmable buffered output 0 from oscillator input port. |+| 40 | OSCout0* | output | Programmable buffered output 0 complement from oscillator input port. |+| 41 | Vcc8 | power_in | Power supply for PLL2 and charge pump 2. |+| 42 | CPout2 | output | Charge pump 2 output for PLL2 loop filter. |+| 43 | Vcc9 | power_in | Power supply for PLL2. |+| 44 | LEuWire | input | MICROWIRE interface latch enable input (CMOS logic level). |+| 45 | CLKuWire | input | MICROWIRE interface clock input (CMOS logic level). |+| 46 | DATAuWire | input | MICROWIRE interface data input (CMOS logic level). |+| 47 | Vcc10 | power_in | Power supply for clock group 3 outputs (CLKout6 and CLKout7). |+| 48 | CLKout6 | output | Programmable clock output 6 (clock group 3). |+| 49 | CLKout6* | output | Programmable clock output 6 complement (clock group 3). |+| 50 | CLKout7* | output | Programmable clock output 7 complement (clock group 3). |+| 51 | CLKout7 | output | Programmable clock output 7 (clock group 3). |+| 52 | Vcc11 | power_in | Power supply for clock group 4 outputs (CLKout8 and CLKout9). |+| 53 | CLKout8 | output | Programmable clock output 8 (clock group 4). |+| 54 | CLKout8* | output | Programmable clock output 8 complement (clock group 4). |+| 55 | CLKout9* | output | Programmable clock output 9 complement (clock group 4). |+| 56 | CLKout9 | output | Programmable clock output 9 (clock group 4). |+| 57 | Vcc12 | power_in | Power supply for clock group 5 outputs (CLKout10 and CLKout11). |+| 58 | CLKout10 | output | Programmable clock output 10 (clock group 5). |+| 59 | CLKout10* | output | Programmable clock output 10 complement (clock group 5). |+| 60 | CLKout11* | output | Programmable clock output 11 complement (clock group 5). |+| 61 | CLKout11 | output | Programmable clock output 11 (clock group 5). |+| 62 | Status_CLKin0 | bidirectional | Programmable status pin; default input for PLL1 reference clock selection, indicates CLKin0 loss-of-signal. |+| 63 | Status_CLKin1 | bidirectional | Programmable status pin; default input for PLL1 reference clock selection, indicates CLKin1 loss-of-signal. |+| 64 | Vcc13 | power_in | Power supply for clock group 0 outputs (CLKout0 and CLKout1). |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-64-EP(9x9) |+| Category | Clock/Timing |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `LMK04808BISQX`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: WQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `lmk04808bisqx-etched.step` / `lmk04808bisqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk04808bisqx.step` / `lmk04808bisqx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk04803) (140 pp, sha256 `6746c180de60df80`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmk04808bisqx-datasheet.pdf)
page.jsonadded+540@@ -0,0 +1,540 @@+{+ "slug": "lmk04808bisqx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "lmk04808bisqx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmk04808bisqx.kicad_sym",+ "lmk04808bisqx.kicad_mod",+ "lmk04808bisqx.glb",+ "lmk04808bisqx.step",+ "lmk04808bisqx.lbr",+ "docs/hero.png",+ "docs/lmk04808bisqx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmk04808bisqx-hero.glb",+ "lmk04808bisqx-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMK04808BISQX",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-64-EP(9x9)",+ "pin_count": 65,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmk04803",+ "parts": {+ "symbol": "lmk04808bisqx.kicad_sym",+ "footprint": "lmk04808bisqx.kicad_mod",+ "model_3d": "lmk04808bisqx-hero.glb",+ "model_3d_plain": "lmk04808bisqx.glb",+ "model_3d_step": "lmk04808bisqx-etched.step",+ "model_3d_step_plain": "lmk04808bisqx.step",+ "lbr": "lmk04808bisqx.lbr"+ },+ "distributor_links": {+ "lcsc": "C1537510"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T08:54:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLKout0",+ "type": "output",+ "description": "Programmable clock output 0 (clock group 0)."+ },+ {+ "number": "2",+ "name": "CLKout0*",+ "type": "output",+ "description": "Programmable clock output 0 complement (clock group 0)."+ },+ {+ "number": "3",+ "name": "CLKout1*",+ "type": "output",+ "description": "Programmable clock output 1 complement (clock group 0)."+ },+ {+ "number": "4",+ "name": "CLKout1",+ "type": "output",+ "description": "Programmable clock output 1 (clock group 0)."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; must be left floating."+ },+ {+ "number": "6",+ "name": "SYNC",+ "type": "bidirectional",+ "description": "Programmable clock output synchronization input or programmable status pin."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; must be left floating."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; must be left floating."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; must be left floating."+ },+ {+ "number": "10",+ "name": "Vcc1",+ "type": "power_in",+ "description": "Power supply for VCO LDO regulator."+ },+ {+ "number": "11",+ "name": "LDObyp1",+ "type": "passive",+ "description": "LDO bypass pin; bypass to ground with 10 µF capacitor."+ },+ {+ "number": "12",+ "name": "LDObyp2",+ "type": "passive",+ "description": "LDO bypass pin; bypass to ground with 0.1 µF capacitor."+ },+ {+ "number": "13",+ "name": "CLKout2",+ "type": "output",+ "description": "Programmable clock output 2 (clock group 1)."+ },+ {+ "number": "14",+ "name": "CLKout2*",+ "type": "output",+ "description": "Programmable clock output 2 complement (clock group 1)."+ },+ {+ "number": "15",+ "name": "CLKout3*",+ "type": "output",+ "description": "Programmable clock output 3 complement (clock group 1)."+ },+ {+ "number": "16",+ "name": "CLKout3",+ "type": "output",+ "description": "Programmable clock output 3 (clock group 1)."+ },+ {+ "number": "17",+ "name": "Vcc2",+ "type": "power_in",+ "description": "Power supply for clock group 1 outputs (CLKout2 and CLKout3)."+ },+ {+ "number": "18",+ "name": "Vcc3",+ "type": "power_in",+ "description": "Power supply for clock group 2 outputs (CLKout4 and CLKout5)."+ },+ {+ "number": "19",+ "name": "CLKout4",+ "type": "output",+ "description": "Programmable clock output 4 (clock group 2)."+ },+ {+ "number": "20",+ "name": "CLKout4*",+ "type": "output",+ "description": "Programmable clock output 4 complement (clock group 2)."+ },+ {+ "number": "21",+ "name": "CLKout5*",+ "type": "output",+ "description": "Programmable clock output 5 complement (clock group 2)."+ },+ {+ "number": "22",+ "name": "CLKout5",+ "type": "output",+ "description": "Programmable clock output 5 (clock group 2)."+ },+ {+ "number": "23",+ "name": "GND",+ "type": "power_in",+ "description": "Ground connection."+ },+ {+ "number": "24",+ "name": "Vcc4",+ "type": "power_in",+ "description": "Power supply for digital circuitry."+ },+ {+ "number": "25",+ "name": "FBCLKin/Fin/CLKin1",+ "type": "input",+ "description": "Reference clock input port 1 for PLL1 (AC or DC coupled); functions as feedback input in 0-delay mode or external VCO input."+ },+ {+ "number": "26",+ "name": "FBCLKin*/Fin*/CLKin1*",+ "type": "input",+ "description": "Reference clock input port 1 complement for PLL1 (AC or DC coupled)."+ },+ {+ "number": "27",+ "name": "Status_Holdover",+ "type": "bidirectional",+ "description": "Programmable status pin; default readback output, programmable as holdover mode indicator."+ },+ {+ "number": "28",+ "name": "CLKin0",+ "type": "input",+ "description": "Reference clock input port 0 for PLL1 (AC or DC coupled)."+ },+ {+ "number": "29",+ "name": "CLKin0*",+ "type": "input",+ "description": "Reference clock input port 0 complement for PLL1 (AC or DC coupled)."+ },+ {+ "number": "30",+ "name": "Vcc5",+ "type": "power_in",+ "description": "Power supply for clock inputs and OSCout1 output."+ },+ {+ "number": "31",+ "name": "OSCout1",+ "type": "output",+ "description": "LVPECL buffered output 1 from oscillator input port."+ },+ {+ "number": "32",+ "name": "OSCout1*",+ "type": "output",+ "description": "LVPECL buffered output 1 complement from oscillator input port."+ },+ {+ "number": "33",+ "name": "Status_LD",+ "type": "bidirectional",+ "description": "Programmable status pin; default lock detect for PLL1 and PLL2."+ },+ {+ "number": "34",+ "name": "CPout1",+ "type": "output",+ "description": "Charge pump 1 output for PLL1 loop filter."+ },+ {+ "number": "35",+ "name": "Vcc6",+ "type": "power_in",+ "description": "Power supply for PLL1 and charge pump 1."+ },+ {+ "number": "36",+ "name": "OSCin",+ "type": "input",+ "description": "Oscillator input for feedback to PLL1 and reference to PLL2 (AC coupled)."+ },+ {+ "number": "37",+ "name": "OSCin*",+ "type": "input",+ "description": "Oscillator input complement for feedback to PLL1 and reference to PLL2 (AC coupled)."+ },+ {+ "number": "38",+ "name": "Vcc7",+ "type": "power_in",+ "description": "Power supply for oscillator input, OSCout0 output, and PLL2 circuitry."+ },+ {+ "number": "39",+ "name": "OSCout0",+ "type": "output",+ "description": "Programmable buffered output 0 from oscillator input port."+ },+ {+ "number": "40",+ "name": "OSCout0*",+ "type": "output",+ "description": "Programmable buffered output 0 complement from oscillator input port."+ },+ {+ "number": "41",+ "name": "Vcc8",+ "type": "power_in",+ "description": "Power supply for PLL2 and charge pump 2."+ },+ {+ "number": "42",+ "name": "CPout2",+ "type": "output",+ "description": "Charge pump 2 output for PLL2 loop filter."+ },+ {+ "number": "43",+ "name": "Vcc9",+ "type": "power_in",+ "description": "Power supply for PLL2."+ },+ {+ "number": "44",+ "name": "LEuWire",+ "type": "input",+ "description": "MICROWIRE interface latch enable input (CMOS logic level)."+ },+ {+ "number": "45",+ "name": "CLKuWire",+ "type": "input",+ "description": "MICROWIRE interface clock input (CMOS logic level)."+ },+ {+ "number": "46",+ "name": "DATAuWire",+ "type": "input",+ "description": "MICROWIRE interface data input (CMOS logic level)."+ },+ {+ "number": "47",+ "name": "Vcc10",+ "type": "power_in",+ "description": "Power supply for clock group 3 outputs (CLKout6 and CLKout7)."+ },+ {+ "number": "48",+ "name": "CLKout6",+ "type": "output",+ "description": "Programmable clock output 6 (clock group 3)."+ },+ {+ "number": "49",+ "name": "CLKout6*",+ "type": "output",+ "description": "Programmable clock output 6 complement (clock group 3)."+ },+ {+ "number": "50",+ "name": "CLKout7*",+ "type": "output",+ "description": "Programmable clock output 7 complement (clock group 3)."+ },+ {+ "number": "51",+ "name": "CLKout7",+ "type": "output",+ "description": "Programmable clock output 7 (clock group 3)."+ },+ {+ "number": "52",+ "name": "Vcc11",+ "type": "power_in",+ "description": "Power supply for clock group 4 outputs (CLKout8 and CLKout9)."+ },+ {+ "number": "53",+ "name": "CLKout8",+ "type": "output",+ "description": "Programmable clock output 8 (clock group 4)."+ },+ {+ "number": "54",+ "name": "CLKout8*",+ "type": "output",+ "description": "Programmable clock output 8 complement (clock group 4)."+ },+ {+ "number": "55",+ "name": "CLKout9*",+ "type": "output",+ "description": "Programmable clock output 9 complement (clock group 4)."+ },+ {+ "number": "56",+ "name": "CLKout9",+ "type": "output",+ "description": "Programmable clock output 9 (clock group 4)."+ },+ {+ "number": "57",+ "name": "Vcc12",+ "type": "power_in",+ "description": "Power supply for clock group 5 outputs (CLKout10 and CLKout11)."+ },+ {+ "number": "58",+ "name": "CLKout10",+ "type": "output",+ "description": "Programmable clock output 10 (clock group 5)."+ },+ {+ "number": "59",+ "name": "CLKout10*",+ "type": "output",+ "description": "Programmable clock output 10 complement (clock group 5)."+ },+ {+ "number": "60",+ "name": "CLKout11*",+ "type": "output",+ "description": "Programmable clock output 11 complement (clock group 5)."+ },+ {+ "number": "61",+ "name": "CLKout11",+ "type": "output",+ "description": "Programmable clock output 11 (clock group 5)."+ },+ {+ "number": "62",+ "name": "Status_CLKin0",+ "type": "bidirectional",+ "description": "Programmable status pin; default input for PLL1 reference clock selection, indicates CLKin0 loss-of-signal."+ },+ {+ "number": "63",+ "name": "Status_CLKin1",+ "type": "bidirectional",+ "description": "Programmable status pin; default input for PLL1 reference clock selection, indicates CLKin1 loss-of-signal."+ },+ {+ "number": "64",+ "name": "Vcc13",+ "type": "power_in",+ "description": "Power supply for clock group 0 outputs (CLKout0 and CLKout1)."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 65 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 59,+ "cost_usd": 0.4409,+ "at": "2026-10-07T08:54:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmk04803",+ "pages": 140,+ "sha256": "6746c180de60df80",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmk04808bisqx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmk04808bisqx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9e8ba63586ec73469cc75553b20eec7220c6826369fd21ec1347a58384a2189b",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}