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LMK03033CISQX
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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# LMK03033CISQX++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · WQFN-48(7x7)++LMK03033CISQX from Texas Instruments, in a WQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground pin for the device; the datasheet lists it as Ground in Table 2-1. |+| 2 | Fout | output | Internal VCO frequency output, enabled only when the EN_Fout bit is set to 1 (default is disabled). |+| 3 | Vcc1 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 4 | CLKuWire | input | MICROWIRE clock input for programming the control registers. |+| 5 | DATAuWire | input | MICROWIRE data input for programming the control registers. |+| 6 | LEuWire | input | MICROWIRE latch enable input for programming the control registers. |+| 7 | NC | unconnected | No connection; leave this pin unconnected. |+| 8 | Vcc2 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 9 | LDObyp1 | passive | LDO bypass pin; connects to the LDO bypass network (paired with LDObyp2). |+| 10 | LDObyp2 | passive | LDO bypass pin; connects to the LDO bypass network (paired with LDObyp1). |+| 11 | GOE | input | Global output enable; when low, all clock outputs are disabled regardless of the individual CLKoutX_EN bits. |+| 12 | LD | output | Lock detect and test output; its mode is set by the PLL_MUX[3:0] register bits (default Hi-Z, disabled). |+| 13 | Vcc3 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 14 | CLKout0 | output | LVDS clock output 0 (true). |+| 15 | CLKout0* | output | LVDS clock output 0 (complementary). |+| 16 | Vcc4 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 17 | CLKout1 | output | LVDS clock output 1 (true). |+| 18 | CLKout1* | output | LVDS clock output 1 (complementary). |+| 19 | Vcc5 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 20 | CLKout2 | output | LVDS clock output 2 (true). |+| 21 | CLKout2* | output | LVDS clock output 2 (complementary). |+| 22 | Vcc6 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 23 | CLKout3 | output | Clock output 3 (true); LVDS for the LMK03033C, LVPECL for other parts in the family. |+| 24 | CLKout3* | output | Clock output 3 (complementary); LVDS for the LMK03033C, LVPECL for other parts in the family. |+| 25 | GND | power_in | Ground pin for the device; the datasheet lists it as Ground in Table 2-1. |+| 26 | Vcc7 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 27 | SYNC* | input | Global clock output synchronization input (active low per the * suffix). |+| 28 | OSCin | input | Oscillator clock input; should be AC coupled. |+| 29 | OSCin* | input | Complementary oscillator clock input; should be AC coupled. |+| 30 | Vcc8 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 31 | Vcc9 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 32 | CPout | output | Charge pump output for the PLL loop filter. |+| 33 | Vcc10 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 34 | NC | unconnected | No connection; leave this pin unconnected. |+| 35 | NC | unconnected | No connection; leave this pin unconnected. |+| 36 | Bias | input | Bias bypass pin for the internal bias circuitry; requires its bypass connection as described in the application section. |+| 37 | Vcc11 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 38 | CLKout4 | output | LVPECL clock output 4 (true). |+| 39 | CLKout4* | output | LVPECL clock output 4 (complementary). |+| 40 | Vcc12 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 41 | CLKout5 | output | LVPECL clock output 5 (true). |+| 42 | CLKout5* | output | LVPECL clock output 5 (complementary). |+| 43 | Vcc13 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 44 | CLKout6 | output | LVPECL clock output 6 (true). |+| 45 | CLKout6* | output | LVPECL clock output 6 (complementary). |+| 46 | Vcc14 | power_in | Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical). |+| 47 | CLKout7 | output | LVPECL clock output 7 (true). |+| 48 | CLKout7* | output | LVPECL clock output 7 (complementary). |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-48(7x7) |+| Category | Clock/Timing |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `LMK03033CISQX`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: WQFN-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `lmk03033cisqx-etched.step` / `lmk03033cisqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk03033cisqx.step` / `lmk03033cisqx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk03000) (48 pp, sha256 `0cf7a425324a1ad2`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmk03033cisqx-datasheet.pdf)
page.jsonadded+445@@ -0,0 +1,445 @@+{+ "slug": "lmk03033cisqx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "lmk03033cisqx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmk03033cisqx.kicad_sym",+ "lmk03033cisqx.kicad_mod",+ "lmk03033cisqx.glb",+ "lmk03033cisqx.step",+ "lmk03033cisqx.lbr",+ "docs/hero.png",+ "docs/lmk03033cisqx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmk03033cisqx-hero.glb",+ "lmk03033cisqx-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMK03033CISQX",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-48(7x7)",+ "pin_count": 49,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmk03000",+ "parts": {+ "symbol": "lmk03033cisqx.kicad_sym",+ "footprint": "lmk03033cisqx.kicad_mod",+ "model_3d": "lmk03033cisqx-hero.glb",+ "model_3d_plain": "lmk03033cisqx.glb",+ "model_3d_step": "lmk03033cisqx-etched.step",+ "model_3d_step_plain": "lmk03033cisqx.step",+ "lbr": "lmk03033cisqx.lbr"+ },+ "distributor_links": {+ "lcsc": "C3607272"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:07:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin for the device; the datasheet lists it as Ground in Table 2-1."+ },+ {+ "number": "2",+ "name": "Fout",+ "type": "output",+ "description": "Internal VCO frequency output, enabled only when the EN_Fout bit is set to 1 (default is disabled)."+ },+ {+ "number": "3",+ "name": "Vcc1",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "4",+ "name": "CLKuWire",+ "type": "input",+ "description": "MICROWIRE clock input for programming the control registers."+ },+ {+ "number": "5",+ "name": "DATAuWire",+ "type": "input",+ "description": "MICROWIRE data input for programming the control registers."+ },+ {+ "number": "6",+ "name": "LEuWire",+ "type": "input",+ "description": "MICROWIRE latch enable input for programming the control registers."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave this pin unconnected."+ },+ {+ "number": "8",+ "name": "Vcc2",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "9",+ "name": "LDObyp1",+ "type": "passive",+ "description": "LDO bypass pin; connects to the LDO bypass network (paired with LDObyp2)."+ },+ {+ "number": "10",+ "name": "LDObyp2",+ "type": "passive",+ "description": "LDO bypass pin; connects to the LDO bypass network (paired with LDObyp1)."+ },+ {+ "number": "11",+ "name": "GOE",+ "type": "input",+ "description": "Global output enable; when low, all clock outputs are disabled regardless of the individual CLKoutX_EN bits."+ },+ {+ "number": "12",+ "name": "LD",+ "type": "output",+ "description": "Lock detect and test output; its mode is set by the PLL_MUX[3:0] register bits (default Hi-Z, disabled)."+ },+ {+ "number": "13",+ "name": "Vcc3",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "14",+ "name": "CLKout0",+ "type": "output",+ "description": "LVDS clock output 0 (true)."+ },+ {+ "number": "15",+ "name": "CLKout0*",+ "type": "output",+ "description": "LVDS clock output 0 (complementary)."+ },+ {+ "number": "16",+ "name": "Vcc4",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "17",+ "name": "CLKout1",+ "type": "output",+ "description": "LVDS clock output 1 (true)."+ },+ {+ "number": "18",+ "name": "CLKout1*",+ "type": "output",+ "description": "LVDS clock output 1 (complementary)."+ },+ {+ "number": "19",+ "name": "Vcc5",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "20",+ "name": "CLKout2",+ "type": "output",+ "description": "LVDS clock output 2 (true)."+ },+ {+ "number": "21",+ "name": "CLKout2*",+ "type": "output",+ "description": "LVDS clock output 2 (complementary)."+ },+ {+ "number": "22",+ "name": "Vcc6",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "23",+ "name": "CLKout3",+ "type": "output",+ "description": "Clock output 3 (true); LVDS for the LMK03033C, LVPECL for other parts in the family."+ },+ {+ "number": "24",+ "name": "CLKout3*",+ "type": "output",+ "description": "Clock output 3 (complementary); LVDS for the LMK03033C, LVPECL for other parts in the family."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin for the device; the datasheet lists it as Ground in Table 2-1."+ },+ {+ "number": "26",+ "name": "Vcc7",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "27",+ "name": "SYNC*",+ "type": "input",+ "description": "Global clock output synchronization input (active low per the * suffix)."+ },+ {+ "number": "28",+ "name": "OSCin",+ "type": "input",+ "description": "Oscillator clock input; should be AC coupled."+ },+ {+ "number": "29",+ "name": "OSCin*",+ "type": "input",+ "description": "Complementary oscillator clock input; should be AC coupled."+ },+ {+ "number": "30",+ "name": "Vcc8",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "31",+ "name": "Vcc9",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "32",+ "name": "CPout",+ "type": "output",+ "description": "Charge pump output for the PLL loop filter."+ },+ {+ "number": "33",+ "name": "Vcc10",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "34",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave this pin unconnected."+ },+ {+ "number": "35",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave this pin unconnected."+ },+ {+ "number": "36",+ "name": "Bias",+ "type": "input",+ "description": "Bias bypass pin for the internal bias circuitry; requires its bypass connection as described in the application section."+ },+ {+ "number": "37",+ "name": "Vcc11",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "38",+ "name": "CLKout4",+ "type": "output",+ "description": "LVPECL clock output 4 (true)."+ },+ {+ "number": "39",+ "name": "CLKout4*",+ "type": "output",+ "description": "LVPECL clock output 4 (complementary)."+ },+ {+ "number": "40",+ "name": "Vcc12",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "41",+ "name": "CLKout5",+ "type": "output",+ "description": "LVPECL clock output 5 (true)."+ },+ {+ "number": "42",+ "name": "CLKout5*",+ "type": "output",+ "description": "LVPECL clock output 5 (complementary)."+ },+ {+ "number": "43",+ "name": "Vcc13",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "44",+ "name": "CLKout6",+ "type": "output",+ "description": "LVPECL clock output 6 (true)."+ },+ {+ "number": "45",+ "name": "CLKout6*",+ "type": "output",+ "description": "LVPECL clock output 6 (complementary)."+ },+ {+ "number": "46",+ "name": "Vcc14",+ "type": "power_in",+ "description": "Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical)."+ },+ {+ "number": "47",+ "name": "CLKout7",+ "type": "output",+ "description": "LVPECL clock output 7 (true)."+ },+ {+ "number": "48",+ "name": "CLKout7*",+ "type": "output",+ "description": "LVPECL clock output 7 (complementary)."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The provided text is a 13-page excerpt of a 48-page datasheet that covers the whole LMK03000 family.; Pin 23/24 (CLKout3/CLKout3*) output type differs by family member. The datasheet says LVDS for LMK03; Pin types were mapped to KiCad ERC classes from the datasheet's I/O column. The Vcc pins, GND, and D",+ "exposed pad 49 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.1029,+ "at": "2026-10-08T18:07:31"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmk03000",+ "pages": 48,+ "sha256": "0cf7a425324a1ad2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmk03033cisqx.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmk03033cisqx-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "769e8119fb9819e4eedf64031ec075fde580d7b6d3e15bd5f3e464aa20f182ab",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}