component
LM98620VHB
Public Made by Adomby adom
Texas Instruments Video Interface ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+116@@ -0,0 +1,116 @@+# LM98620VHB++**Texas Instruments** · Video Interface ICs · TQFP-80(12x12)++LM98620VHB from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SHD/HOLD | input | Data clamp pulse/hold input used for once-per-pixel sample timing. |+| 2 | VDDD | power_in | Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS. |+| 3 | VSSD | power_in | Digital power supply ground. |+| 4 | CLPIN | input | Input pulse that invokes the input clamp switch. |+| 5 | BLKCLP | input | Input pulse that invokes the black calibration loop, with an internal 108 kΩ pull-down to VSSD. |+| 6 | AGC_ONB | input | Input pulse that invokes the white calibration loop; pulse low to initiate white clamp (active low), tie high to disable, internal 108 kΩ pull-up to VDDD. |+| 7 | OVPB | input | Over-voltage protection enable (active low) that switches OS inputs to ground during power-up, to be tied high after AFE and CCD voltages have stabilized. |+| 8 | MCLK | input | Master clock input. |+| 9 | GPI1 | input | General-purpose input 1, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13). |+| 10 | GPI2 | input | General-purpose input 2, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13). |+| 11 | GPI3 | input | General-purpose input 3, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13). |+| 12 | GPI4 | input | General-purpose input 4, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13). |+| 13 | GPI5 | input | General-purpose input 5, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13). |+| 14 | VSSD | power_in | Digital power supply ground. |+| 15 | VDDD | power_in | Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS. |+| 16 | IBIAS | passive | Optional IBIAS resistor connection; connect an 11 kΩ 1% resistor to VSSA to minimize device-to-device power variation. |+| 17 | VREG1 | power_out | Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 18 | VSSD | power_in | Digital power supply ground. |+| 19 | VDDD | power_in | Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS. |+| 20 | VREG2 | power_out | Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 21 | TXCLK1+ | output | Positive leg of differential LVDS output clock 1. |+| 22 | TXCLK1- | output | Negative leg of differential LVDS output clock 1. |+| 23 | TXOUTC1+ | output | Positive leg of differential LVDS output data C1. |+| 24 | TXOUTC1- | output | Negative leg of differential LVDS output data C1. |+| 25 | TXOUTB1+ | output | Positive leg of differential LVDS output data B1. |+| 26 | TXOUTB1- | output | Negative leg of differential LVDS output data B1. |+| 27 | VREG2 | power_out | Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 28 | VSSLVDS | power_in | LVDS power supply ground. |+| 29 | TXOUTA1+ | output | Positive leg of differential LVDS output data A1. |+| 30 | TXOUTA1- | output | Negative leg of differential LVDS output data A1. |+| 31 | TXCLK2+ | output | Positive leg of differential LVDS output clock 2. |+| 32 | TXCLK2- | output | Negative leg of differential LVDS output clock 2. |+| 33 | VREG2 | power_out | Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 34 | VSSLVDS | power_in | LVDS power supply ground. |+| 35 | TXOUTC2+ | output | Positive leg of differential LVDS output data C2. |+| 36 | TXOUTC2- | output | Negative leg of differential LVDS output data C2. |+| 37 | TXOUTB2+ | output | Positive leg of differential LVDS output data B2. |+| 38 | TXOUTB2- | output | Negative leg of differential LVDS output data B2. |+| 39 | TXOUTA2+ | output | Positive leg of differential LVDS output data A2. |+| 40 | TXOUTA2- | output | Negative leg of differential LVDS output data A2. |+| 41 | VSSLVDS | power_in | LVDS power supply ground. |+| 42 | VSSLVDS | power_in | LVDS power supply ground. |+| 43 | VREG2 | power_out | Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 44 | VDDLVDS | power_in | LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD. |+| 45 | VDDLVDS | power_in | LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD. |+| 46 | VREG1 | power_out | Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed). |+| 47 | TESTO_1 | output | Digital test output. |+| 48 | TESTO_0 | output | Digital test output. |+| 49 | RESETB | input | Master reset input, active low, with an internal 108 kΩ pull-up to VDDD. |+| 50 | SCLK | input | Serial clock for the 4-wire serial interface. |+| 51 | SDI | input | Serial data input for the 4-wire serial interface. |+| 52 | SENB | input | Serial enable for the 4-wire serial interface, active low, with an internal 108 kΩ pull-up to VDDD. |+| 53 | SDO | output | Serial output data for the 4-wire serial interface. |+| 54 | VDDD | power_in | Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS. |+| 55 | VSSD | power_in | Digital power supply ground. |+| 56 | VSSA | power_in | Analog power supply ground. |+| 57 | VREF | power_in | Reference voltage bypass, approx. 1.2 V output (voltage provided for debugging only, not guaranteed). |+| 58 | VDDA | power_in | Analog power supply, 3.0 V to 3.6 V. |+| 59 | VREFTOUT | output | Top reference bypass, approx. 2.23 V output; connect to bypass capacitors and VREFTINx (voltage provided for debugging only, not guaranteed). |+| 60 | VREFBOUT | output | Bottom reference bypass, approx. 0.98 V output; connect to bypass capacitors and VREFBINx (voltage provided for debugging only, not guaranteed). |+| 61 | VREFBIN2 | input | Bottom reference input voltage for the ADC; connect to VREFBOUT. |+| 62 | VREFTIN2 | input | Top reference input voltage for the ADC; connect to VREFTOUT. |+| 63 | VREFBIN1 | input | Bottom reference input voltage for the AFE; connect to VREFBOUT. |+| 64 | VREFTIN1 | input | Top reference input voltage for the AFE; connect to VREFTOUT. |+| 65 | VSSA | power_in | Analog power supply ground. |+| 66 | OSR1 | input | Input voltage 1 for the red channel. |+| 67 | VDDA | power_in | Analog power supply, 3.0 V to 3.6 V. |+| 68 | OSR2 | input | Input voltage 2 for the red channel. |+| 69 | VSSA | power_in | Analog power supply ground. |+| 70 | OSG1 | input | Input voltage 1 for the green channel. |+| 71 | VDDA | power_in | Analog power supply, 3.0 V to 3.6 V. |+| 72 | OSG2 | input | Input voltage 2 for the green channel. |+| 73 | VSSA | power_in | Analog power supply ground. |+| 74 | OSB1 | input | Input voltage 1 for the blue channel. |+| 75 | VDDA | power_in | Analog power supply, 3.0 V to 3.6 V. |+| 76 | OSB2 | input | Input voltage 2 for the blue channel. |+| 77 | VSSA | power_in | Analog power supply ground. |+| 78 | VCLP_EXT | input | External clamp voltage; connect to VCLP_INT or a customer-supplied reference voltage. |+| 79 | VCLP_INT | output | Internally generated V-clamp voltage, approx. 1.65 V output; connect to bypass capacitors and VCLP_EXT (voltage provided for debugging only, not guaranteed). |+| 80 | SHP/SAMPLE | input | Pedestal clamp pulse/sample input used for once-per-pixel sample timing. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-80(12x12) |+| Category | Interface |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `LM98620VHB`+- Footprint: `Package_QFP:TQFP-80_12x12mm_P0.5mm`+- 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)+- 3D model files: `lm98620vhb-etched.step` / `lm98620vhb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm98620vhb.step` / `lm98620vhb.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm98620) (71 pp, sha256 `e6098b8fe4d2438f`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm98620vhb-datasheet.pdf)
page.jsonadded+629@@ -0,0 +1,629 @@+{+ "slug": "lm98620vhb",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Video Interface ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "lm98620vhb",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lm98620vhb.kicad_sym",+ "lm98620vhb.kicad_mod",+ "lm98620vhb.glb",+ "lm98620vhb.step",+ "lm98620vhb.lbr",+ "docs/hero.png",+ "docs/lm98620vhb-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lm98620vhb-hero.glb",+ "lm98620vhb-hero.overlay.json"+ ],+ "component": {+ "mpn": "LM98620VHB",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-80(12x12)",+ "pin_count": 80,+ "category": "Interface",+ "subcategory": "Video Interface ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lm98620",+ "parts": {+ "symbol": "lm98620vhb.kicad_sym",+ "footprint": "lm98620vhb.kicad_mod",+ "model_3d": "lm98620vhb-hero.glb",+ "model_3d_plain": "lm98620vhb.glb",+ "model_3d_step": "lm98620vhb-etched.step",+ "model_3d_step_plain": "lm98620vhb.step",+ "lbr": "lm98620vhb.lbr"+ },+ "distributor_links": {+ "lcsc": "C1554444"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:43:45Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SHD/HOLD",+ "type": "input",+ "description": "Data clamp pulse/hold input used for once-per-pixel sample timing."+ },+ {+ "number": "2",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS."+ },+ {+ "number": "3",+ "name": "VSSD",+ "type": "power_in",+ "description": "Digital power supply ground."+ },+ {+ "number": "4",+ "name": "CLPIN",+ "type": "input",+ "description": "Input pulse that invokes the input clamp switch."+ },+ {+ "number": "5",+ "name": "BLKCLP",+ "type": "input",+ "description": "Input pulse that invokes the black calibration loop, with an internal 108 kΩ pull-down to VSSD."+ },+ {+ "number": "6",+ "name": "AGC_ONB",+ "type": "input",+ "description": "Input pulse that invokes the white calibration loop; pulse low to initiate white clamp (active low), tie high to disable, internal 108 kΩ pull-up to VDDD."+ },+ {+ "number": "7",+ "name": "OVPB",+ "type": "input",+ "description": "Over-voltage protection enable (active low) that switches OS inputs to ground during power-up, to be tied high after AFE and CCD voltages have stabilized."+ },+ {+ "number": "8",+ "name": "MCLK",+ "type": "input",+ "description": "Master clock input."+ },+ {+ "number": "9",+ "name": "GPI1",+ "type": "input",+ "description": "General-purpose input 1, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13)."+ },+ {+ "number": "10",+ "name": "GPI2",+ "type": "input",+ "description": "General-purpose input 2, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13)."+ },+ {+ "number": "11",+ "name": "GPI3",+ "type": "input",+ "description": "General-purpose input 3, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13)."+ },+ {+ "number": "12",+ "name": "GPI4",+ "type": "input",+ "description": "General-purpose input 4, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13)."+ },+ {+ "number": "13",+ "name": "GPI5",+ "type": "input",+ "description": "General-purpose input 5, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13)."+ },+ {+ "number": "14",+ "name": "VSSD",+ "type": "power_in",+ "description": "Digital power supply ground."+ },+ {+ "number": "15",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS."+ },+ {+ "number": "16",+ "name": "IBIAS",+ "type": "passive",+ "description": "Optional IBIAS resistor connection; connect an 11 kΩ 1% resistor to VSSA to minimize device-to-device power variation."+ },+ {+ "number": "17",+ "name": "VREG1",+ "type": "power_out",+ "description": "Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "18",+ "name": "VSSD",+ "type": "power_in",+ "description": "Digital power supply ground."+ },+ {+ "number": "19",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS."+ },+ {+ "number": "20",+ "name": "VREG2",+ "type": "power_out",+ "description": "Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "21",+ "name": "TXCLK1+",+ "type": "output",+ "description": "Positive leg of differential LVDS output clock 1."+ },+ {+ "number": "22",+ "name": "TXCLK1-",+ "type": "output",+ "description": "Negative leg of differential LVDS output clock 1."+ },+ {+ "number": "23",+ "name": "TXOUTC1+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data C1."+ },+ {+ "number": "24",+ "name": "TXOUTC1-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data C1."+ },+ {+ "number": "25",+ "name": "TXOUTB1+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data B1."+ },+ {+ "number": "26",+ "name": "TXOUTB1-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data B1."+ },+ {+ "number": "27",+ "name": "VREG2",+ "type": "power_out",+ "description": "Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "28",+ "name": "VSSLVDS",+ "type": "power_in",+ "description": "LVDS power supply ground."+ },+ {+ "number": "29",+ "name": "TXOUTA1+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data A1."+ },+ {+ "number": "30",+ "name": "TXOUTA1-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data A1."+ },+ {+ "number": "31",+ "name": "TXCLK2+",+ "type": "output",+ "description": "Positive leg of differential LVDS output clock 2."+ },+ {+ "number": "32",+ "name": "TXCLK2-",+ "type": "output",+ "description": "Negative leg of differential LVDS output clock 2."+ },+ {+ "number": "33",+ "name": "VREG2",+ "type": "power_out",+ "description": "Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "34",+ "name": "VSSLVDS",+ "type": "power_in",+ "description": "LVDS power supply ground."+ },+ {+ "number": "35",+ "name": "TXOUTC2+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data C2."+ },+ {+ "number": "36",+ "name": "TXOUTC2-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data C2."+ },+ {+ "number": "37",+ "name": "TXOUTB2+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data B2."+ },+ {+ "number": "38",+ "name": "TXOUTB2-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data B2."+ },+ {+ "number": "39",+ "name": "TXOUTA2+",+ "type": "output",+ "description": "Positive leg of differential LVDS output data A2."+ },+ {+ "number": "40",+ "name": "TXOUTA2-",+ "type": "output",+ "description": "Negative leg of differential LVDS output data A2."+ },+ {+ "number": "41",+ "name": "VSSLVDS",+ "type": "power_in",+ "description": "LVDS power supply ground."+ },+ {+ "number": "42",+ "name": "VSSLVDS",+ "type": "power_in",+ "description": "LVDS power supply ground."+ },+ {+ "number": "43",+ "name": "VREG2",+ "type": "power_out",+ "description": "Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "44",+ "name": "VDDLVDS",+ "type": "power_in",+ "description": "LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD."+ },+ {+ "number": "45",+ "name": "VDDLVDS",+ "type": "power_in",+ "description": "LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD."+ },+ {+ "number": "46",+ "name": "VREG1",+ "type": "power_out",+ "description": "Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "47",+ "name": "TESTO_1",+ "type": "output",+ "description": "Digital test output."+ },+ {+ "number": "48",+ "name": "TESTO_0",+ "type": "output",+ "description": "Digital test output."+ },+ {+ "number": "49",+ "name": "RESETB",+ "type": "input",+ "description": "Master reset input, active low, with an internal 108 kΩ pull-up to VDDD."+ },+ {+ "number": "50",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock for the 4-wire serial interface."+ },+ {+ "number": "51",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input for the 4-wire serial interface."+ },+ {+ "number": "52",+ "name": "SENB",+ "type": "input",+ "description": "Serial enable for the 4-wire serial interface, active low, with an internal 108 kΩ pull-up to VDDD."+ },+ {+ "number": "53",+ "name": "SDO",+ "type": "output",+ "description": "Serial output data for the 4-wire serial interface."+ },+ {+ "number": "54",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS."+ },+ {+ "number": "55",+ "name": "VSSD",+ "type": "power_in",+ "description": "Digital power supply ground."+ },+ {+ "number": "56",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog power supply ground."+ },+ {+ "number": "57",+ "name": "VREF",+ "type": "power_in",+ "description": "Reference voltage bypass, approx. 1.2 V output (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "58",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply, 3.0 V to 3.6 V."+ },+ {+ "number": "59",+ "name": "VREFTOUT",+ "type": "output",+ "description": "Top reference bypass, approx. 2.23 V output; connect to bypass capacitors and VREFTINx (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "60",+ "name": "VREFBOUT",+ "type": "output",+ "description": "Bottom reference bypass, approx. 0.98 V output; connect to bypass capacitors and VREFBINx (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "61",+ "name": "VREFBIN2",+ "type": "input",+ "description": "Bottom reference input voltage for the ADC; connect to VREFBOUT."+ },+ {+ "number": "62",+ "name": "VREFTIN2",+ "type": "input",+ "description": "Top reference input voltage for the ADC; connect to VREFTOUT."+ },+ {+ "number": "63",+ "name": "VREFBIN1",+ "type": "input",+ "description": "Bottom reference input voltage for the AFE; connect to VREFBOUT."+ },+ {+ "number": "64",+ "name": "VREFTIN1",+ "type": "input",+ "description": "Top reference input voltage for the AFE; connect to VREFTOUT."+ },+ {+ "number": "65",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog power supply ground."+ },+ {+ "number": "66",+ "name": "OSR1",+ "type": "input",+ "description": "Input voltage 1 for the red channel."+ },+ {+ "number": "67",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply, 3.0 V to 3.6 V."+ },+ {+ "number": "68",+ "name": "OSR2",+ "type": "input",+ "description": "Input voltage 2 for the red channel."+ },+ {+ "number": "69",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog power supply ground."+ },+ {+ "number": "70",+ "name": "OSG1",+ "type": "input",+ "description": "Input voltage 1 for the green channel."+ },+ {+ "number": "71",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply, 3.0 V to 3.6 V."+ },+ {+ "number": "72",+ "name": "OSG2",+ "type": "input",+ "description": "Input voltage 2 for the green channel."+ },+ {+ "number": "73",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog power supply ground."+ },+ {+ "number": "74",+ "name": "OSB1",+ "type": "input",+ "description": "Input voltage 1 for the blue channel."+ },+ {+ "number": "75",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply, 3.0 V to 3.6 V."+ },+ {+ "number": "76",+ "name": "OSB2",+ "type": "input",+ "description": "Input voltage 2 for the blue channel."+ },+ {+ "number": "77",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog power supply ground."+ },+ {+ "number": "78",+ "name": "VCLP_EXT",+ "type": "input",+ "description": "External clamp voltage; connect to VCLP_INT or a customer-supplied reference voltage."+ },+ {+ "number": "79",+ "name": "VCLP_INT",+ "type": "output",+ "description": "Internally generated V-clamp voltage, approx. 1.65 V output; connect to bypass capacitors and VCLP_EXT (voltage provided for debugging only, not guaranteed)."+ },+ {+ "number": "80",+ "name": "SHP/SAMPLE",+ "type": "input",+ "description": "Pedestal clamp pulse/sample input used for once-per-pixel sample timing."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet groups GPI1-5 on pins 9 to 13 without stating which GPI goes on which pin. I assigned ; The datasheet gives differential LVDS pairs as a single pin range (for example TXCLK1 on pins 21, 22; The datasheet classifies IBIAS as analog output (AO) but describes it as a resistor connection to VS"+ ],+ "pages_sent": 12,+ "cost_usd": 0.1233,+ "at": "2026-10-08T15:43:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm98620",+ "pages": 71,+ "sha256": "e6098b8fe4d2438f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm98620vhb.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "77f4de0ca0c787b8b4416c735fddfcecf5cf4cea0ca3550f96f5c47c8664594c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm98620vhb-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b829f0016de907a9d868b46d9fae9b08f96910b4c96b8101a0a774f5404b719f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}