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LM5155QDSSTQ1
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Texas Instruments DC-DC Controllers, WSON-12-EP(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# LM5155QDSSTQ1++**Texas Instruments** · DC-DC Controllers · WSON-12-EP(2x3)++LM5155QDSSTQ1 from Texas Instruments, in a WSON-12-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BIAS | power_in | Supply input for the internal VCC regulator; connect a bypass capacitor between this pin and PGND, with BIAS rated 3.5V to 45V (2.97V to 16V when tied to VCC) and 50V absolute maximum. |+| 2 | VCC | power_out | Output of the internal VCC regulator and supply input for the MOSFET driver; connect a ceramic bypass capacitor between this pin and PGND, with a recommended value of 1µF to 4.7µF and VCC regulation of 6.85V typical. |+| 3 | GATE | output | Gate drive output for the N-channel MOSFET, connected through a short, low-inductance path directly to the MOSFET gate, capable of sinking or sourcing 1.5A peak. |+| 4 | PGND | power_in | Power ground, connected through a wide, short, low-inductance path directly to the ground connection of the current sense resistor. |+| 5 | CS | input | Current sense input, connected through a short path to the positive side of the current sense resistor, with a 100mV (±7%) current limit threshold referenced to PGND. |+| 6 | COMP | output | Output of the internal transconductance error amplifier; connect the loop compensation network between this pin and PGND, with the COMP pin voltage clamped internally. |+| 7 | AGND | power_in | Analog ground, connected through a wide, short path to the analog ground plane; the exposed pad must be tied to AGND. |+| 8 | FB | input | Inverting input of the error amplifier, fed from the output resistor divider with a 1V reference and a 3.8V absolute maximum rating; the low-side feedback resistor connects to AGND. |+| 9 | SS | input | Soft-start timing pin; an external capacitor to AGND and the internal 10µA current source set the ramp rate of the internal error amplifier reference, with a 3.8V absolute maximum rating. |+| 10 | RT | input | Switching frequency set pin; a single resistor between RT and AGND programs the switching frequency from 100kHz to 2.2MHz, with the RT regulator holding this pin at 0.5V when enabled. |+| 11 | PGOOD | output | Open-drain power-good indicator that goes low when FB is below the undervoltage threshold; connect a pull-up resistor to the system rail (minimum 10kΩ recommended) and do not exceed VBIAS + 0.3V. |+| 12 | UVLO/EN/SYNC | input | Line undervoltage lockout programming pin set by a resistor divider from the supply, which also accepts negative pulses for clock synchronization; it must not be left floating and should be connected to BIAS when unused. |+| 13 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WSON-12-EP(2x3) |+| Category | Power Supply Chip |+| Pins | 13 |++## CAD (KiCad official)++- Symbol: `LM5155QDSSTQ1`+- Footprint: `Package_SON:WSON-12-1EP_3x2mm_P0.5mm_EP1x2.65`+- 3D model: WSON-12-EP(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `lm5155qdsstq1-etched.step` / `lm5155qdsstq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5155qdsstq1.step` / `lm5155qdsstq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5155-q1) (50 pp, sha256 `a8503f9fa4bec785`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5155qdsstq1-datasheet.pdf)
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connect a bypass capacitor between this pin and PGND, with BIAS rated 3.5V to 45V (2.97V to 16V when tied to VCC) and 50V absolute maximum."+ },+ {+ "number": "2",+ "name": "VCC",+ "type": "power_out",+ "description": "Output of the internal VCC regulator and supply input for the MOSFET driver; connect a ceramic bypass capacitor between this pin and PGND, with a recommended value of 1µF to 4.7µF and VCC regulation of 6.85V typical."+ },+ {+ "number": "3",+ "name": "GATE",+ "type": "output",+ "description": "Gate drive output for the N-channel MOSFET, connected through a short, low-inductance path directly to the MOSFET gate, capable of sinking or sourcing 1.5A peak."+ },+ {+ "number": "4",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground, connected through a wide, short, low-inductance path directly to the ground connection of the current sense resistor."+ },+ {+ "number": "5",+ "name": "CS",+ "type": "input",+ "description": "Current sense input, connected through a short path to the positive side of the current sense resistor, with a 100mV (±7%) current limit threshold referenced to PGND."+ },+ {+ "number": "6",+ "name": "COMP",+ "type": "output",+ "description": "Output of the internal transconductance error amplifier; connect the loop compensation network between this pin and PGND, with the COMP pin voltage clamped internally."+ },+ {+ "number": "7",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground, connected through a wide, short path to the analog ground plane; the exposed pad must be tied to AGND."+ },+ {+ "number": "8",+ "name": "FB",+ "type": "input",+ "description": "Inverting input of the error amplifier, fed from the output resistor divider with a 1V reference and a 3.8V absolute maximum rating; the low-side feedback resistor connects to AGND."+ },+ {+ "number": "9",+ "name": "SS",+ "type": "input",+ "description": "Soft-start timing pin; an external capacitor to AGND and the internal 10µA current source set the ramp rate of the internal error amplifier reference, with a 3.8V absolute maximum rating."+ },+ {+ "number": "10",+ "name": "RT",+ "type": "input",+ "description": "Switching frequency set pin; a single resistor between RT and AGND programs the switching frequency from 100kHz to 2.2MHz, with the RT regulator holding this pin at 0.5V when enabled."+ },+ {+ "number": "11",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good indicator that goes low when FB is below the undervoltage threshold; connect a pull-up resistor to the system rail (minimum 10kΩ recommended) and do not exceed VBIAS + 0.3V."+ },+ {+ "number": "12",+ "name": "UVLO/EN/SYNC",+ "type": "input",+ "description": "Line undervoltage lockout programming pin set by a resistor divider from the supply, which also accepts negative pulses for clock synchronization; it must not be left floating and should be connected to BIAS when unused."+ },+ {+ "number": "13",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed pad is labeled 'EP' in the pin figure and table with no numeric pin number, so it is lis; The datasheet pin table gives types P, O, G, I (and P for VCC). These were mapped to KiCad classes: ; The MPN LM5155QDSSTQ1 is the wettable-flank variant (DSS0012C, WF) according to the device compariso",+ "exposed pad 13 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 29,+ "cost_usd": 0.1449,+ "at": "2026-10-08T00:56:28"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5155-q1",+ "pages": 50,+ "sha256": "a8503f9fa4bec785",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 13,+ "described": 13,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm5155qdsstq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.02,+ 3,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "56aafd469c50a379182be2f348b23e35708e25b50fa504c41b8efe1ab31a11c4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm5155qdsstq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.02,+ 3,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0c45e907ce4a41c275d9bd363594992e5d526e1c6b509605ab1178d3ff3b6f64",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}