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LM5143QRHARQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# LM5143QRHARQ1++**Texas Instruments** · DC-DC Converters · VQFN-40(6x6)++LM5143QRHARQ1 from Texas Instruments, in a VQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SS2 | input | Channel 2 soft start programming pin; external capacitor and 20μA current source set soft start ramp duration; pulling below 150mV disables channel 2 gate drivers. |+| 2 | COMP2 | output | Channel 2 transconductance error amplifier output for external loop compensation network. |+| 3 | FB2 | input | Channel 2 feedback input; connect to VDDA for 3.3V fixed output, AGND for 5V fixed output, or external voltage divider for 0.6V to 55V adjustable with 0.6V regulation threshold. |+| 4 | CS2 | input | Channel 2 current sense amplifier input; connect via low-current Kelvin connection to external current sense resistor or DCR sensing network. |+| 5 | VOUT2 | input | Channel 2 output voltage sense and current sense amplifier input; connect to current sense resistor output side or DCR sensing capacitor terminal. |+| 6 | VCCX | power_in | Optional external bias supply input; when VCCX exceeds 4.3V, internal VCC regulator disables and VCCX connects internally to VCC; do not exceed 6.5V or go below -0.3V. |+| 7 | PG2 | output | Open-drain power-good output that goes low when VOUT2 falls below 92% or rises above 110% of regulation point; 25μs glitch filter prevents false trips. |+| 8 | HOL2 | output | Channel 2 high-side gate driver turn-off output; drives high to disable high-side MOSFET. |+| 9 | HO2 | output | Channel 2 high-side gate driver turn-on output with 3.25A peak pull current and self-adaptive dead-time control; voltage swing HB to SW relative to SW. |+| 10 | SW2 | power_in | Channel 2 buck regulator switch node connecting high-side MOSFET source, low-side MOSFET drain, and bootstrap capacitor; operating range -0.3V to 65V nominal, -5V to 70V absolute maximum. |+| 11 | HB2 | power_in | Channel 2 bootstrap gate driver power supply; operating range -0.3V to 5.25V relative to SW2 node; connect 0.1μF ceramic capacitor between HB2 and SW2. |+| 12 | LOL2 | output | Channel 2 low-side gate driver turn-off output; drives high to disable low-side MOSFET. |+| 13 | LO2 | output | Channel 2 low-side gate driver turn-on output with 4.25A peak sink current and self-adaptive dead-time control relative to PGND2. |+| 14 | PGND2 | power_in | Power ground return for channel 2 low-side NMOS gate driver; must connect to system ground plane and PCB return path. |+| 15 | VCC | power_in | VCC bias supply pins (pins 15 and 16 must be connected together on PCB); internal 5V regulator with 4.7V to 5.3V output, 3.3V UVLO threshold, and 170mA current limit. |+| 16 | VCC | power_in | VCC bias supply pins (pins 15 and 16 must be connected together on PCB); internal 5V regulator with 4.7V to 5.3V output, 3.3V UVLO threshold, and 170mA current limit. |+| 17 | PGND1 | power_in | Power ground return for channel 1 low-side NMOS gate driver; must connect to system ground plane and PCB return path. |+| 18 | LO1 | output | Channel 1 low-side gate driver turn-on output with 4.25A peak sink current and self-adaptive dead-time control relative to PGND1. |+| 19 | LOL1 | output | Channel 1 low-side gate driver turn-off output; drives high to disable low-side MOSFET. |+| 20 | HB1 | power_in | Channel 1 bootstrap gate driver power supply; operating range -0.3V to 5.25V relative to SW1 node; connect 0.1μF ceramic capacitor between HB1 and SW1. |+| 21 | SW1 | power_in | Channel 1 buck regulator switch node connecting high-side MOSFET source, low-side MOSFET drain, and bootstrap capacitor; operating range -0.3V to 65V nominal, -5V to 70V absolute maximum. |+| 22 | HO1 | output | Channel 1 high-side gate driver turn-on output with 3.25A peak pull current and self-adaptive dead-time control; voltage swing HB to SW relative to SW. |+| 23 | HOL1 | output | Channel 1 high-side gate driver turn-off output; drives high to disable high-side MOSFET. |+| 24 | PG1 | output | Open-drain power-good output that goes low when VOUT1 falls below 92% or rises above 110% of regulation point; 25μs glitch filter prevents false trips. |+| 25 | VIN | power_in | Power supply voltage input source for internal VCC regulator; operating range 3.5V to 65V recommended, -0.3V to 70V absolute maximum; VCC regulator reduces input when VIN < 5V. |+| 26 | VOUT1 | input | Channel 1 output voltage sense and current sense amplifier input; connect to current sense resistor output side or DCR sensing capacitor terminal. |+| 27 | CS1 | input | Channel 1 current sense amplifier input; connect via low-current Kelvin connection to external current sense resistor or DCR sensing network. |+| 28 | FB1 | input | Channel 1 feedback input; connect to VDDA for 3.3V fixed output, AGND for 5V fixed output, or external voltage divider for 0.6V to 55V adjustable with 0.6V regulation threshold. |+| 29 | COMP1 | output | Channel 1 transconductance error amplifier output for external loop compensation; gm = 1200μS in normal mode or gm = 60μS in ultra-low IQ mode. |+| 30 | SS1 | input | Channel 1 soft start programming pin; external capacitor and 20μA current source set soft start ramp duration; pulling below 150mV disables channel 1 gate drivers. |+| 31 | EN1 | input | Active-high enable input for channel 1; threshold >2V enables output, <0.4V disables output; can accept input voltage up to 70V; do not leave floating. |+| 32 | RES | output | Restart timer pin for hiccup mode configuration; external capacitor sets hiccup protection delay time using 20μA charging current; pulled low when 512 consecutive cycle limit events detected. |+| 33 | DEMB | input | Diode emulation/synchronization input pin; connect to AGND for DCM diode emulation mode, VDDA for FPWM mode, or apply external clock (up to 2.5MHz) for frequency synchronization. |+| 34 | MODE | input | Mode selection pin; connect to AGND for dual output 1200μS transconductance operation, or 10kΩ resistor to AGND for ultra-low IQ 60μS operation. |+| 35 | AGND | power_in | Analog ground connection for internal voltage reference and analog circuits; must establish single-point connection to system ground at exposed pad location. |+| 36 | VDDA | power_out | Internal analog bias regulator output providing 4.75V to 5.25V; connect 470nF ceramic decoupling capacitor between VDDA and AGND for low-noise bias rail. |+| 37 | RT | input | Frequency programming pin; external resistor to AGND sets oscillator frequency using equation fSW(MHz) = 22/RRT(kΩ) for range 100kHz to 2.2MHz. |+| 38 | DITH | input | Dither control pin; external capacitor with 20μA charging current enables frequency dither modulation at ±5% around programmed frequency; connect to VDDA during power-up to disable dither. |+| 39 | SYNCOUT | output | Synchronization output providing 90° phase-lagging logic-level signal relative to HO2; use for cascading multiple LM5143A-Q1 controllers or external phase distribution. |+| 40 | EN2 | input | Active-high enable input for channel 2; threshold >2V enables output, <0.4V disables output; can accept input voltage up to 70V; do not leave floating. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40(6x6) |+| Category | Power Management (PMIC) |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `LM5143QRHARQ1`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40(6x6) (KiCad packages3D, STEP)+- 3D model files: `lm5143qrharq1-etched.step` / `lm5143qrharq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5143qrharq1.step` / `lm5143qrharq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5143a-q1) (73 pp, sha256 `2815ac02b2daae78`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5143qrharq1-datasheet.pdf)
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external capacitor and 20μA current source set soft start ramp duration; pulling below 150mV disables channel 2 gate drivers."+ },+ {+ "number": "2",+ "name": "COMP2",+ "type": "output",+ "description": "Channel 2 transconductance error amplifier output for external loop compensation network."+ },+ {+ "number": "3",+ "name": "FB2",+ "type": "input",+ "description": "Channel 2 feedback input; connect to VDDA for 3.3V fixed output, AGND for 5V fixed output, or external voltage divider for 0.6V to 55V adjustable with 0.6V regulation threshold."+ },+ {+ "number": "4",+ "name": "CS2",+ "type": "input",+ "description": "Channel 2 current sense amplifier input; connect via low-current Kelvin connection to external current sense resistor or DCR sensing network."+ },+ {+ "number": "5",+ "name": "VOUT2",+ "type": "input",+ "description": "Channel 2 output voltage sense and current sense amplifier input; connect to current sense resistor output side or DCR sensing capacitor terminal."+ },+ {+ "number": "6",+ "name": "VCCX",+ "type": "power_in",+ "description": "Optional external bias supply input; when VCCX exceeds 4.3V, internal VCC regulator disables and VCCX connects internally to VCC; do not exceed 6.5V or go below -0.3V."+ },+ {+ "number": "7",+ "name": "PG2",+ "type": "output",+ "description": "Open-drain power-good output that goes low when VOUT2 falls below 92% or rises above 110% of regulation point; 25μs glitch filter prevents false trips."+ },+ {+ "number": "8",+ "name": "HOL2",+ "type": "output",+ "description": "Channel 2 high-side gate driver turn-off output; drives high to disable high-side MOSFET."+ },+ {+ "number": "9",+ "name": "HO2",+ "type": "output",+ "description": "Channel 2 high-side gate driver turn-on output with 3.25A peak pull current and self-adaptive dead-time control; voltage swing HB to SW relative to SW."+ },+ {+ "number": "10",+ "name": "SW2",+ "type": "power_in",+ "description": "Channel 2 buck regulator switch node connecting high-side MOSFET source, low-side MOSFET drain, and bootstrap capacitor; operating range -0.3V to 65V nominal, -5V to 70V absolute maximum."+ },+ {+ "number": "11",+ "name": "HB2",+ "type": "power_in",+ "description": "Channel 2 bootstrap gate driver power supply; operating range -0.3V to 5.25V relative to SW2 node; connect 0.1μF ceramic capacitor between HB2 and SW2."+ },+ {+ "number": "12",+ "name": "LOL2",+ "type": "output",+ "description": "Channel 2 low-side gate driver turn-off output; drives high to disable low-side MOSFET."+ },+ {+ "number": "13",+ "name": "LO2",+ "type": "output",+ "description": "Channel 2 low-side gate driver turn-on output with 4.25A peak sink current and self-adaptive dead-time control relative to PGND2."+ },+ {+ "number": "14",+ "name": "PGND2",+ "type": "power_in",+ "description": "Power ground return for channel 2 low-side NMOS gate driver; must connect to system ground plane and PCB return path."+ },+ {+ "number": "15",+ "name": "VCC",+ "type": "power_in",+ "description": "VCC bias supply pins (pins 15 and 16 must be connected together on PCB); internal 5V regulator with 4.7V to 5.3V output, 3.3V UVLO threshold, and 170mA current limit."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "VCC bias supply pins (pins 15 and 16 must be connected together on PCB); internal 5V regulator with 4.7V to 5.3V output, 3.3V UVLO threshold, and 170mA current limit."+ },+ {+ "number": "17",+ "name": "PGND1",+ "type": "power_in",+ "description": "Power ground return for channel 1 low-side NMOS gate driver; must connect to system ground plane and PCB return path."+ },+ {+ "number": "18",+ "name": "LO1",+ "type": "output",+ "description": "Channel 1 low-side gate driver turn-on output with 4.25A peak sink current and self-adaptive dead-time control relative to PGND1."+ },+ {+ "number": "19",+ "name": "LOL1",+ "type": "output",+ "description": "Channel 1 low-side gate driver turn-off output; drives high to disable low-side MOSFET."+ },+ {+ "number": "20",+ "name": "HB1",+ "type": "power_in",+ "description": "Channel 1 bootstrap gate driver power supply; operating range -0.3V to 5.25V relative to SW1 node; connect 0.1μF ceramic capacitor between HB1 and SW1."+ },+ {+ "number": "21",+ "name": "SW1",+ "type": "power_in",+ "description": "Channel 1 buck regulator switch node connecting high-side MOSFET source, low-side MOSFET drain, and bootstrap capacitor; operating range -0.3V to 65V nominal, -5V to 70V absolute maximum."+ },+ {+ "number": "22",+ "name": "HO1",+ "type": "output",+ "description": "Channel 1 high-side gate driver turn-on output with 3.25A peak pull current and self-adaptive dead-time control; voltage swing HB to SW relative to SW."+ },+ {+ "number": "23",+ "name": "HOL1",+ "type": "output",+ "description": "Channel 1 high-side gate driver turn-off output; drives high to disable high-side MOSFET."+ },+ {+ "number": "24",+ "name": "PG1",+ "type": "output",+ "description": "Open-drain power-good output that goes low when VOUT1 falls below 92% or rises above 110% of regulation point; 25μs glitch filter prevents false trips."+ },+ {+ "number": "25",+ "name": "VIN",+ "type": "power_in",+ "description": "Power supply voltage input source for internal VCC regulator; operating range 3.5V to 65V recommended, -0.3V to 70V absolute maximum; VCC regulator reduces input when VIN < 5V."+ },+ {+ "number": "26",+ "name": "VOUT1",+ "type": "input",+ "description": "Channel 1 output voltage sense and current sense amplifier input; connect to current sense resistor output side or DCR sensing capacitor terminal."+ },+ {+ "number": "27",+ "name": "CS1",+ "type": "input",+ "description": "Channel 1 current sense amplifier input; connect via low-current Kelvin connection to external current sense resistor or DCR sensing network."+ },+ {+ "number": "28",+ "name": "FB1",+ "type": "input",+ "description": "Channel 1 feedback input; connect to VDDA for 3.3V fixed output, AGND for 5V fixed output, or external voltage divider for 0.6V to 55V adjustable with 0.6V regulation threshold."+ },+ {+ "number": "29",+ "name": "COMP1",+ "type": "output",+ "description": "Channel 1 transconductance error amplifier output for external loop compensation; gm = 1200μS in normal mode or gm = 60μS in ultra-low IQ mode."+ },+ {+ "number": "30",+ "name": "SS1",+ "type": "input",+ "description": "Channel 1 soft start programming pin; external capacitor and 20μA current source set soft start ramp duration; pulling below 150mV disables channel 1 gate drivers."+ },+ {+ "number": "31",+ "name": "EN1",+ "type": "input",+ "description": "Active-high enable input for channel 1; threshold >2V enables output, <0.4V disables output; can accept input voltage up to 70V; do not leave floating."+ },+ {+ "number": "32",+ "name": "RES",+ "type": "output",+ "description": "Restart timer pin for hiccup mode configuration; external capacitor sets hiccup protection delay time using 20μA charging current; pulled low when 512 consecutive cycle limit events detected."+ },+ {+ "number": "33",+ "name": "DEMB",+ "type": "input",+ "description": "Diode emulation/synchronization input pin; connect to AGND for DCM diode emulation mode, VDDA for FPWM mode, or apply external clock (up to 2.5MHz) for frequency synchronization."+ },+ {+ "number": "34",+ "name": "MODE",+ "type": "input",+ "description": "Mode selection pin; connect to AGND for dual output 1200μS transconductance operation, or 10kΩ resistor to AGND for ultra-low IQ 60μS operation."+ },+ {+ "number": "35",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground connection for internal voltage reference and analog circuits; must establish single-point connection to system ground at exposed pad location."+ },+ {+ "number": "36",+ "name": "VDDA",+ "type": "power_out",+ "description": "Internal analog bias regulator output providing 4.75V to 5.25V; connect 470nF ceramic decoupling capacitor between VDDA and AGND for low-noise bias rail."+ },+ {+ "number": "37",+ "name": "RT",+ "type": "input",+ "description": "Frequency programming pin; external resistor to AGND sets oscillator frequency using equation fSW(MHz) = 22/RRT(kΩ) for range 100kHz to 2.2MHz."+ },+ {+ "number": "38",+ "name": "DITH",+ "type": "input",+ "description": "Dither control pin; external capacitor with 20μA charging current enables frequency dither modulation at ±5% around programmed frequency; connect to VDDA during power-up to disable dither."+ },+ {+ "number": "39",+ "name": "SYNCOUT",+ "type": "output",+ "description": "Synchronization output providing 90° phase-lagging logic-level signal relative to HO2; use for cascading multiple LM5143A-Q1 controllers or external phase distribution."+ },+ {+ "number": "40",+ "name": "EN2",+ "type": "input",+ "description": "Active-high enable input for channel 2; threshold >2V enables output, <0.4V disables output; can accept input voltage up to 70V; do not leave floating."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: SW1 and SW2 are high-voltage switch nodes that conduct power and can swing significantly in voltage ; VCC pins 15 and 16 must be connected together on the PCB per datasheet requirement. Separation could; VOUT1 and VOUT2 are feedback sense inputs (not the actual regulator outputs); they monitor external ",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 33,+ "cost_usd": 0.3211,+ "at": "2026-10-05T21:06:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5143a-q1",+ "pages": 73,+ "sha256": "2815ac02b2daae78",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}