component
LM5117QPMHE
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+58@@ -0,0 +1,58 @@+# LM5117QPMHE++**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP++LM5117QPMHE from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | UVLO | input | Undervoltage lockout programming pin: below 0.4 V the regulator is shut down, 0.4 V to 1.25 V gives standby with no HO/LO switching, and above 1.25 V enables switching, with a 20 µA source through the external UVLO resistors providing hysteresis. |+| 2 | DEMB | input | Optional logic input where low enables diode emulation (low-side NMOS latched off after reverse current is detected) and high disables it, with an internal 50 kΩ pull-down that enables emulation when floating. |+| 3 | RES | output | Restart timer pin that sets the hiccup-mode off time; hiccup begins after 256 consecutive PWM cycles of cycle-by-cycle current limiting, and a 10 µA source then charges the RES capacitor to 1.25 V to restart the controller. |+| 4 | SS | input | Soft-start pin where an external capacitor and an internal 10 µA source set the error amplifier reference ramp rate, and the pin is held low when VCC < 5 V, UVLO < 1.25 V or during thermal shutdown. |+| 5 | RT | input | Oscillator timing pin programmed by a single resistor to AGND, with a recommended maximum oscillator frequency of 750 kHz, and synchronizable to an external clock through a small coupling capacitor. |+| 6 | AGND | power_in | Analog ground and return for the internal 0.8 V voltage reference and analog circuits. |+| 7 | VCCDIS | input | Optional input that disables the internal VCC regulator when above 1.25 V, with an internal 500 kΩ pull-down that keeps the regulator enabled when the pin is floating. |+| 8 | FB | input | Inverting input of the internal error amplifier, where a resistor divider from the output sets the output voltage against a 0.8 V regulation threshold. |+| 9 | COMP | output | Output of the internal error amplifier, with the loop compensation network connected between this pin and FB. |+| 10 | CM | output | Current monitor output that provides the average sensed inductor current, to be monitored between CM and AGND, and left floating when not used. |+| 11 | RAMP | input | PWM ramp input where an external resistor and capacitor between SW, RAMP and AGND set a ramp slope proportional to the input supply voltage. |+| 12 | CS | input | Current sense amplifier input to be connected to the high side of the current sense resistor. |+| 13 | CSG | power_in | Kelvin ground connection to be connected directly to the low side of the current sense resistor. |+| 14 | PGND | power_in | Power ground return for the low-side NMOS gate driver, to be connected directly to the low side of the current sense resistor. |+| 15 | LO | output | Low-side NMOS gate drive output, to be connected to the synchronous low-side gate through a short, low-inductance path. |+| 16 | VCC | power_in | Bias supply pin that should be decoupled to PGND with a low ESR/ESL capacitor placed as close to the controller as possible. |+| 17 | SW | output | Switching node of the buck regulator, connected to the bootstrap capacitor, high-side NMOS source and low-side NMOS drain through a short, low-inductance path. |+| 18 | HO | output | High-side NMOS gate drive output, to be connected to the high-side gate through a short, low-inductance path. |+| 19 | HB | power_in | High-side driver supply for the bootstrap gate drive, connected to the external bootstrap diode cathode and bootstrap capacitor, placed as close to the controller as possible. |+| 20 | VIN | power_in | Supply voltage input for the VCC regulator, with VIN to AGND rated at −0.3 V to 75 V absolute maximum and 5.5 V to 65 V recommended. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-20-EP |+| Category | Power Management (PMIC) |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `LM5117QPMHE`+- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`+- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `lm5117qpmhe-etched.step` / `lm5117qpmhe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5117qpmhe.step` / `lm5117qpmhe.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5117) (49 pp, sha256 `9e27f24e84faebf5`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5117qpmhe-datasheet.pdf)
page.jsonadded+277@@ -0,0 +1,277 @@+{+ "slug": "lm5117qpmhe",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, HTSSOP-20-EP. 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hiccup begins after 256 consecutive PWM cycles of cycle-by-cycle current limiting, and a 10 µA source then charges the RES capacitor to 1.25 V to restart the controller."+ },+ {+ "number": "4",+ "name": "SS",+ "type": "input",+ "description": "Soft-start pin where an external capacitor and an internal 10 µA source set the error amplifier reference ramp rate, and the pin is held low when VCC < 5 V, UVLO < 1.25 V or during thermal shutdown."+ },+ {+ "number": "5",+ "name": "RT",+ "type": "input",+ "description": "Oscillator timing pin programmed by a single resistor to AGND, with a recommended maximum oscillator frequency of 750 kHz, and synchronizable to an external clock through a small coupling capacitor."+ },+ {+ "number": "6",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground and return for the internal 0.8 V voltage reference and analog circuits."+ },+ {+ "number": "7",+ "name": "VCCDIS",+ "type": "input",+ "description": "Optional input that disables the internal VCC regulator when above 1.25 V, with an internal 500 kΩ pull-down that keeps the regulator enabled when the pin is floating."+ },+ {+ "number": "8",+ "name": "FB",+ "type": "input",+ "description": "Inverting input of the internal error amplifier, where a resistor divider from the output sets the output voltage against a 0.8 V regulation threshold."+ },+ {+ "number": "9",+ "name": "COMP",+ "type": "output",+ "description": "Output of the internal error amplifier, with the loop compensation network connected between this pin and FB."+ },+ {+ "number": "10",+ "name": "CM",+ "type": "output",+ "description": "Current monitor output that provides the average sensed inductor current, to be monitored between CM and AGND, and left floating when not used."+ },+ {+ "number": "11",+ "name": "RAMP",+ "type": "input",+ "description": "PWM ramp input where an external resistor and capacitor between SW, RAMP and AGND set a ramp slope proportional to the input supply voltage."+ },+ {+ "number": "12",+ "name": "CS",+ "type": "input",+ "description": "Current sense amplifier input to be connected to the high side of the current sense resistor."+ },+ {+ "number": "13",+ "name": "CSG",+ "type": "power_in",+ "description": "Kelvin ground connection to be connected directly to the low side of the current sense resistor."+ },+ {+ "number": "14",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground return for the low-side NMOS gate driver, to be connected directly to the low side of the current sense resistor."+ },+ {+ "number": "15",+ "name": "LO",+ "type": "output",+ "description": "Low-side NMOS gate drive output, to be connected to the synchronous low-side gate through a short, low-inductance path."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Bias supply pin that should be decoupled to PGND with a low ESR/ESL capacitor placed as close to the controller as possible."+ },+ {+ "number": "17",+ "name": "SW",+ "type": "output",+ "description": "Switching node of the buck regulator, connected to the bootstrap capacitor, high-side NMOS source and low-side NMOS drain through a short, low-inductance path."+ },+ {+ "number": "18",+ "name": "HO",+ "type": "output",+ "description": "High-side NMOS gate drive output, to be connected to the high-side gate through a short, low-inductance path."+ },+ {+ "number": "19",+ "name": "HB",+ "type": "power_in",+ "description": "High-side driver supply for the bootstrap gate drive, connected to the external bootstrap diode cathode and bootstrap capacitor, placed as close to the controller as possible."+ },+ {+ "number": "20",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply voltage input for the VCC regulator, with VIN to AGND rated at −0.3 V to 75 V absolute maximum and 5.5 V to 65 V recommended."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout is taken from the HTSSOP (PWP) column of the Pin Functions table, which the datasheet pai; The datasheet covers both LM5117 and LM5117-Q1. The HTSSOP pin table is shared between them, but the; The text extraction garbled the Type column for some pins (PGND, LO, HO, VCC, HB, VIN). Types were a",+ "exposed pad 21 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 10,+ "cost_usd": 0.0811,+ "at": "2026-10-07T22:31:43"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5117",+ "pages": 49,+ "sha256": "9e27f24e84faebf5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm5117qpmhe.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "de4b41bded9be3af13ce2d9bfc9b6d88c2c08a5ca88aba13e30ccbe9ca9ddbf1",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm5117qpmhe-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "18963e54e440010fb011abe251f8a66679d401507481dcffe8faba1c243c76a7",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}