← Commit history

Publish 0.2.0

Ray ·4a77a83e15 · ·parent 5fefb48
3 files changed +24−7
README.md+14
@@ -37,6 +37,20 @@ LGS5145EP from Legend Si, in a ESOP-8. Pinout and pin descriptions extracted fro - Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm` - 3D model: ESOP-8 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`lgs5145ep.step`](lgs5145ep.step) | 193 KB | You want the bare part, or you mark your own boards. |+| [`lgs5145ep-etched.step`](lgs5145ep-etched.step) | 1.5 MB | You want the part with `LGS5145EP` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 398 faces against 63 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "lgs5145ep",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "Legend Si DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+9−6
@@ -4,7 +4,7 @@   "slug": "lgs5145ep",   "title": "LGS5145EP",   "brief": "Legend Si DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -34,13 +34,13 @@         "number": "1",         "name": "BST",         "type": "passive",-        "description": "Bootstrap supply pin for the high-side gate driver. A high-quality 100nF ceramic capacitor must be connected between BST and SW to bias the internal high-side MOSFET gate driver. Observe capacitor voltage rating (\u226516V recommended)."+        "description": "Bootstrap supply pin for the high-side gate driver. A high-quality 100nF ceramic capacitor must be connected between BST and SW to bias the internal high-side MOSFET gate driver. Observe capacitor voltage rating (≥16V recommended)."       },       {         "number": "2",         "name": "VIN",         "type": "power_in",-        "description": "Regulator power input, 4.5V-60V. Bypass with a 2.2\u00b5F (or larger) ceramic capacitor placed as close as possible between VIN and GND to minimize ringing and EMI."+        "description": "Regulator power input, 4.5V-60V. Bypass with a 2.2µF (or larger) ceramic capacitor placed as close as possible between VIN and GND to minimize ringing and EMI."       },       {         "number": "3",@@ -58,7 +58,7 @@         "number": "5",         "name": "FB",         "type": "input",-        "description": "Feedback input to the internal error amplifier. Connect to the tap of an external resistor divider from VOUT to GND; internal reference is 0.812V. VOUT = 0.812 \u00d7 (RF + RG)/RG; keep RG \u2264 30k\u03a9. Absolute max FB voltage is -0.3V to 6V."+        "description": "Feedback input to the internal error amplifier. Connect to the tap of an external resistor divider from VOUT to GND; internal reference is 0.812V. VOUT = 0.812 × (RF + RG)/RG; keep RG ≤ 30kΩ. Absolute max FB voltage is -0.3V to 6V."       },       {         "number": "6",@@ -157,6 +157,9 @@     "docs/hero.png",     "docs/lgs5145ep-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"-  ]+    "viewers/footprint.html",+    "pads.json"+  ],+  "description": "Legend Si DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "visibility": "public" }\ No newline at end of file