L6599DTR

@@ -0,0 +1,57 @@+# L6599DTR++**STMicroelectronics** · AC-DC Controllers and Regulators · SOIC-16++L6599DTR from STMicroelectronics, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CSS | passive | Soft-start pin. External capacitor to GND and resistor to RFmin (pin 4) set the maximum oscillator frequency and the frequency-shift time constant during start-up. Internally discharged whenever the chip turns OFF (VCC<UVLO, LINE<1.25V or >6V, DIS>1.85V, ISEN>1.5V, DELAY>3.5V) and while ISEN exceeds 0.8V (down to 0.75V) so the part always soft-starts. |+| 2 | DELAY | passive | Delayed shutdown upon overcurrent. External RC to GND sets the maximum duration of an OCP condition (charged by an internal 150 uA current source when ISEN>0.8V) and the restart delay. IC stops switching once the pin reaches 3.5V and re-enables when the voltage falls below 0.3V, yielding hiccup-mode short-circuit protection. |+| 3 | CF | passive | Timing capacitor. Charged/discharged by internal current sources programmed by the RFmin network to set the converter switching frequency. |+| 4 | RFmin | passive | Minimum oscillator frequency setting. Provides a precise 2 V reference; the resistor to GND sets the minimum oscillator frequency. The optocoupler phototransistor is coupled here through a resistor to modulate the operating frequency (feedback), and an RC series to GND sets the soft-start frequency shift. |+| 5 | STBY | input | Burst-mode operation threshold. Compared to an internal 1.25 V reference with 50 mV hysteresis; when the feedback-related voltage falls below the reference, the IC enters idle (burst) mode and drops to reduced quiescent current. Tie to RFmin if burst-mode is not used. |+| 6 | ISEN | input | Current-sense input for two-level OCP. Above the 0.8 V threshold (50 mV hysteresis) the soft-start cap is discharged, shifting the switching frequency up to limit power. A second 1.5 V comparator latches the device off (near-zero consumption) if the current keeps rising; latch clears when VCC drops below UVLO. Tie to GND if unused. |+| 7 | LINE | input | Line-sensing input for AC/DC brownout protection. Below 1.25 V the IC shuts down (not latched), consumption drops and the soft-start cap discharges; operation re-enables above 1.25 V. Internal 15 uA current source provides hysteresis while pin is below 1.25 V. An internal zener top-limits the pin; triggering it latches the IC OFF. Bias between 1.25 V and 6 V if unused; bypass to GND for noise immunity. |+| 8 | DIS | input | Latched device shutdown. When the pin exceeds 1.85 V the IC is latched OFF at near-zero consumption; latch cleared only by recycling VCC below UVLO. Enables easy OTP/OVP implementation. Tie to GND if unused. |+| 9 | PFC_STOP | output | Open-drain ON/OFF control for the upstream PFC controller. Pulled low when the IC is shut down (DIS>1.85V, ISEN>1.5V, LINE>6V, STBY<1.25V or DELAY>2V) and re-opens after DELAY falls below 0.3V. Open during UVLO. Leave unconnected if unused. |+| 10 | GND | power_in | Chip signal/low-side driver ground. All bias-component grounds should return here on a dedicated track kept separate from any pulsed current return. |+| 11 | LVG | output | Low-side gate-drive output for the half-bridge lower MOSFET. Capable of 0.3 A min source / 0.8 A min sink peak current; actively pulled to GND during UVLO. |+| 12 | VCC | power_in | Supply voltage for the signal section and the low-side gate driver. Operating range 8.85-16 V, turn-ON ~10.7 V, turn-OFF ~8.15 V, VCC clamp ~17 V. A small (0.1 uF typ.) bypass to GND may be useful to keep clean bias for the signal section. |+| 13 | N.C. | unconnected | High-voltage spacer. Not internally connected; isolates the high-voltage pins and eases PCB creepage/safety compliance. |+| 14 | OUT | power_in | High-side gate-drive floating ground and current return for the high-side driver. Rated -3 V to VBOOT-18 V; connects to the half-bridge switching node. Route carefully to avoid large negative spikes. |+| 15 | HVG | output | High-side floating gate-drive output for the half-bridge upper MOSFET. Capable of 0.3 A min source / 0.8 A min sink peak current. An internal resistor to OUT (pin 14) keeps the pin from floating during UVLO. |+| 16 | VBOOT | power_in | High-side gate-drive floating supply. Bootstrap capacitor between VBOOT and OUT (pin 14) is refreshed by an internal synchronous bootstrap DMOS driven in phase with the low-side driver, replacing the external fast-recovery diode. Floating supply rated up to 618 V (max), tested to 580 V leakage. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SOIC-16 |+| Category | PMIC |+| Pins | 16 |++## Ordering variants++- `L6599DTRL6599D`+- `L6599DTR`+- `L6599DTRL6599N`++## CAD (KiCad official)++- Symbol: `L6599DTR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/l6599dtr.pdf) (36 pp, sha256 `d3eec3163e3e5244`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/l6599dtr-datasheet.pdf)

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