component
KSZ8795CLXCC
Public Made by Adomby adom
Microchip Tech Interface - Specialized, LQFP-80(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+183@@ -0,0 +1,183 @@+# KSZ8795CLXCC++**Microchip Tech** · Interface - Specialized · LQFP-80(10x10)++KSZ8795CLXCC from Microchip Tech, in a LQFP-80(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD12A | power_in | 1.2V core power. |+| 2 | VDDAT | power_in | 3.3V or 2.5V analog power. |+| 3 | GNDA | power_in | Analog ground. |+| 4 | RXP1 | input | Port 1 physical receive signal + (differential). |+| 5 | RXM1 | input | Port 1 physical receive signal - (differential). |+| 6 | TXP1 | output | Port 1 physical transmit signal + (differential). |+| 7 | TXM1 | output | Port 1 physical transmit signal - (differential). |+| 8 | RXP2 | input | Port 2 physical receive signal + (differential). |+| 9 | RXM2 | input | Port 2 physical receive signal - (differential). |+| 10 | TXP2 | output | Port 2 physical transmit signal + (differential). |+| 11 | TXM2 | output | Port 2 physical transmit signal - (differential). |+| 12 | VDDAT | power_in | 3.3V or 2.5V analog power. |+| 13 | RXP3 | input | Port 3 physical receive signal + (differential). |+| 14 | RXM3 | input | Port 3 physical receive signal - (differential). |+| 15 | TXP3 | output | Port 3 physical transmit signal + (differential). |+| 16 | TXM3 | output | Port 3 physical transmit signal - (differential). |+| 17 | RXP4 | input | Port 4 physical receive signal + (differential). |+| 18 | RXM4 | input | Port 4 physical receive signal - (differential). |+| 19 | TXP4 | output | Port 4 physical transmit signal + (differential). |+| 20 | TXM4 | output | Port 4 physical transmit signal - (differential). |+| 21 | GNDA | power_in | Analog ground. |+| 22 | NC | unconnected | No connect. |+| 23 | INTR_N | output | Active-low open-drain interrupt output; an external pull-up resistor is needed when in use. |+| 24 | LED3_1 | bidirectional | Port 3 LED indicator 1 (internal pull-up during reset); strap with LED3_0 selects Port 5 GMAC5 mode: 00 MII, 01 RMII, 10 GMII, 11 RGMII (default). |+| 25 | LED3_0 | bidirectional | Port 3 LED indicator 0 (internal pull-up during reset); strap option with LED3_1 for GMAC5 interface mode select. |+| 26 | VDD12D | power_in | 1.2V core power. |+| 27 | GNDD | power_in | Digital ground. |+| 28 | LED4_1 | bidirectional | Port 4 LED indicator 1 (internal pull-up during reset, output otherwise). |+| 29 | TXEN5/TXD5_CTL | input | Port 5 switch transmit enable in GMII/MII/RMII, or transmit data control in RGMII; internal pull-down. |+| 30 | TXD5_0 | input | Port 5 switch transmit bit 0 for GMII/RGMII/MII/RMII; internal pull-down. |+| 31 | LED4_0 | bidirectional | Port 4 LED indicator 0 (internal pull-up during reset, output otherwise). |+| 32 | TXD5_1 | input | Port 5 switch transmit bit 1 for GMII/RGMII/MII/RMII; internal pull-down. |+| 33 | GNDD | power_in | Digital ground. |+| 34 | VDDIO | power_in | 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. |+| 35 | TXD5_2 | input | Port 5 switch transmit bit 2 for GMII/RGMII/MII; no connection in RMII. |+| 36 | TXD5_3 | input | Port 5 switch transmit bit 3 for GMII/RGMII/MII; no connection in RMII. |+| 37 | TXER5 | input | Port 5 switch transmit error for GMII/MII; no connection in RGMII/RMII. |+| 38 | TXD5_4 | input | Port 5 switch transmit bit 4 in GMII only; no connection in RGMII/MII/RMII. |+| 39 | TXD5_5 | input | Port 5 switch transmit bit 5 in GMII only; no connection in RGMII/MII/RMII. |+| 40 | TXD5_6 | input | Port 5 switch transmit bit 6 in GMII only; no connection in RGMII/MII/RMII. |+| 41 | TXD5_7 | input | Port 5 switch transmit bit 7 in GMII only; no connection in RGMII/MII/RMII. |+| 42 | VDD12D | power_in | 1.2V core power. |+| 43 | TXC5/REFCLKI/GTXC5 | bidirectional | Port 5 GMAC5 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz input, GMII/RGMII 125 MHz transmit clock input. |+| 44 | RXC5/GRXC5 | bidirectional | Port 5 GMAC5 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz output, GMII/RGMII 125 MHz receive clock output. |+| 45 | RXD5_0 | bidirectional | Port 5 switch receive bit 0 for GMII/RGMII/MII/RMII; input with pull-down during reset, output otherwise. |+| 46 | RXD5_1 | bidirectional | Port 5 switch receive bit 1 for GMII/RGMII/MII/RMII; input with pull-down during reset, output otherwise. |+| 47 | GNDD | power_in | Digital ground. |+| 48 | VDDIO | power_in | 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. |+| 49 | RXD5_2 | bidirectional | Port 5 switch receive bit 2 for GMII/RGMII/MII; no connection in RMII. |+| 50 | RXD5_3 | bidirectional | Port 5 switch receive bit 3 for GMII/RGMII/MII; no connection in RMII. |+| 51 | RXDV5/CRSDV5/RXD5_CTL | bidirectional | Receive data valid in GMII/MII, CRSDV5 in RMII, or receive data control in RGMII. |+| 52 | RXER5 | bidirectional | Port 5 switch receive error for GMII/MII; no connection in RGMII/RMII. |+| 53 | CRS5 | bidirectional | Port 5 carrier sense for GMII/MII; no connection in RGMII/RMII. |+| 54 | COL5 | bidirectional | Port 5 collision detect for GMII/MII; no connection in RGMII/RMII. |+| 55 | REFCLKO | bidirectional | 25 MHz clock output option, controlled by strap LED2_0 and Global Register 11 bit 1; default enabled, better disabled if unused. |+| 56 | PME_N | bidirectional | Power management event signal indicating a WoL wake-up frame was detected; polarity programmable, default active-low. |+| 57 | RXD5_4 | bidirectional | Port 5 switch receive bit 4 in GMII only; no connection in RGMII/MII/RMII. |+| 58 | RXD5_5 | bidirectional | Port 5 switch receive bit 5 in GMII only; no connection in RGMII/MII/RMII. |+| 59 | RXD5_6 | bidirectional | Port 5 switch receive bit 6 in GMII only; no connection in RGMII/MII/RMII. |+| 60 | RXD5_7 | bidirectional | Port 5 switch receive bit 7 in GMII only; no connection in RGMII/MII/RMII. |+| 61 | GNDD | power_in | Digital ground. |+| 62 | LED2_1 | bidirectional | Port 2 LED indicator 1; strap selects Port 5 GMII/MII MAC/PHY mode (PU MAC default, PD PHY) and RMII clock mode (PU clock mode, PD normal mode). |+| 63 | LED2_0 | bidirectional | Port 2 LED indicator 0; strap enables REFCLKO 25 MHz output (PU enabled default, PD disabled). |+| 64 | LED1_1 | bidirectional | Port 1 LED indicator 1; strap selects PLL clock source (PU use 25 MHz XI/XO, PD use external clock from TXC5 in RMII normal mode). |+| 65 | LED1_0 | bidirectional | Port 1 LED indicator 0; strap selects GMII/RGMII speed (PU 1Gbps default, PD 10/100Mbps). |+| 66 | SPIQ | bidirectional | SPI serial data output in SPI client mode; strap selects serial bus (PD SPI client mode, PU MDC/MDIO mode), external pull-up or pull-down required. |+| 67 | SCL_MDC | input | Clock input for SPI or MDC/MDIO interface, up to 25 MHz. |+| 68 | SDA_MDIO | bidirectional | Serial data input in SPI client mode, or MDC/MDIO data input/output. |+| 69 | SPIS_N | input | Active-low SPI client mode chip select; when high the device is deselected and SPIQ is high impedance. |+| 70 | VDDIO | power_in | 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. |+| 71 | GNDD | power_in | Digital ground. |+| 72 | RST_N | input | Active-low hardware reset input with internal pull-up. |+| 73 | VDD12D | power_in | 1.2V core power. |+| 74 | NC | unconnected | No connect. |+| 75 | ATST | unconnected | No connect; factory test pin. |+| 76 | VDDAT | power_in | 3.3V or 2.5V analog power. |+| 77 | ISET | passive | Sets physical transmit output current; connect to GND through a 12.4 kOhm 1% resistor. |+| 78 | GNDA | power_in | Analog ground. |+| 79 | XI | input | Crystal/oscillator input; 25 MHz crystal or 3.3V oscillator with ±50 ppm tolerance. |+| 80 | XO | output | Crystal clock output; connects to one end of the 25 MHz crystal. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip Tech |+| Package | LQFP-80(10x10) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 80 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply Voltage VDD12A, VDD12D | | -0.5 | | 1.8 | V | | 115 |+| Supply Voltage VDDAT, VDDIO | | -0.5 | | 4 | V | | 115 |+| Input Voltage | | -0.5 | | 4 | V | | 115 |+| Output Voltage | | -0.5 | | 4 | V | | 115 |+| Lead Temperature | | | | 260 | °C | soldering, 10s | 115 |+| Storage Temperature | TS | -55 | | 150 | °C | | 115 |+| Maximum Junction Temperature | | | | 125 | °C | | 115 |+| ESD Rating | | | | 5 | kV | | 115 |+| Supply Voltage VDD12A, VDD12D | | 1.14 | | 1.26 | V | | 115 |+| Supply Voltage VDDAT | VDDAT | 3.135 | | 3.465 | V | VDDAT @ 3.3V | 115 |+| Supply Voltage VDDAT | VDDAT | 2.375 | | 2.625 | V | VDDAT @ 2.5V | 115 |+| Supply Voltage VDDIO | VDDIO | 3.135 | | 3.465 | V | VDDIO @ 3.3V | 115 |+| Supply Voltage VDDIO | VDDIO | 2.375 | | 2.625 | V | VDDIO @ 2.5V | 115 |+| Supply Voltage VDDIO | VDDIO | 1.71 | | 1.89 | V | VDDIO @ 1.8V | 115 |+| Ambient Temperature (Commercial) | TA | 0 | | 70 | °C | Commercial | 115 |+| Package Thermal Resistance | ΘJA | | 55.05 | | °C/W | No heat spreader, air velocity 0m/s | 115 |+| Package Thermal Resistance | ΘJC | | 25.06 | | °C/W | No heat spreader, air velocity 0m/s | 115 |+| Input High Voltage | VIH | 2 | | | V | VDDIO = 3.3V | 116 |+| Input High Voltage | VIH | 1.8 | | | V | VDDIO = 2.5V | 116 |+| Input High Voltage | VIH | 1.3 | | | V | VDDIO = 1.8V | 116 |+| Input Low Voltage | VIL | | | 0.8 | V | VDDIO = 3.3V | 116 |+| Input Low Voltage | VIL | | | 0.7 | V | VDDIO = 2.5V | 116 |+| Input Low Voltage | VIL | | | 0.5 | V | VDDIO = 1.8V | 116 |+| Input Current (Excluding Pull-Up/Pull-Down) | IIN | | | 10 | µA | VIN = GND ~ VDDIO | 116 |+| Output High Voltage | VOH | 2.4 | | | V | VDDIO = 3.3V | 116 |+| Output High Voltage | VOH | 2 | | | V | VDDIO = 2.5V | 116 |+| Output High Voltage | VOH | 1.5 | | | V | VDDIO = 1.8V | 116 |+| Output Low Voltage | VOL | | | 0.4 | V | VDDIO = 3.3V | 117 |+| Output Low Voltage | VOL | | | 0.3 | V | VDDIO = 1.8V | 117 |+| Output Tri-State Leakage | IOZ | | | 10 | µA | VIN = GND ~ VDDIO | 117 |+| 100BASE-TX Peak Differential Output Voltage | VO | 0.95 | | 1.05 | V | 100Ω termination on the differential output | 117 |+| 100BASE-TX Output Voltage Imbalance | VIMB | | | 2 | % | 100Ω termination on the differential output | 117 |+| 100BASE-TX Rise/Fall Time | tr/tf | 3 | | 5 | ns | | 117 |+| 100BASE-TX Rise/Fall Time Imbalance | | 0 | | 0.5 | ns | | 117 |+| 100BASE-TX Duty Cycle Distortion | | -0.5 | | 0.5 | ns | | 117 |+| 100BASE-TX Overshoot | | | | 5 | % | | 117 |+| 100BASE-TX Output Jitters | | 0 | 0.75 | 1.4 | ns | Peak-to-Peak | 117 |+| 10BASE-T Receive Squelch Threshold | VSQ | 300 | 400 | 585 | mV | 5 MHz square wave | 117 |+| 10BASE-T Peak Differential Output Voltage | VP | 2.2 | 2.5 | 2.8 | V | 100Ω termination on the differential output; VDDAT = 3.3V | 117 |+| 10BASE-T Output Jitters | | | 1.4 | 3.5 | ns | Peak-to-Peak; VDDAT = 3.3V | 117 |+| 10BASE-T Rise/Fall Times | | | 28 | 30 | ns | VDDAT = 3.3V | 117 |+| I/O Pin Effective Pull-Up Resistance | R1.8PU | 75 | 95 | 135 | kΩ | VDDIO = 1.8V | 117 |+| I/O Pin Effective Pull-Down Resistance | R1.8PD | 53 | 68 | 120 | kΩ | VDDIO = 1.8V | 117 |+| I/O Pin Effective Pull-Up Resistance | R2.5PU | 46 | 60 | 93 | kΩ | VDDIO = 2.5V | 117 |+| I/O Pin Effective Pull-Down Resistance | R2.5PD | 46 | 59 | 103 | kΩ | VDDIO = 2.5V | 117 |+| I/O Pin Effective Pull-Up Resistance | R3.3PU | 35 | 45 | 65 | kΩ | VDDIO = 3.3V | 117 |+| I/O Pin Effective Pull-Down Resistance | R3.3PD | 37 | 46 | 74 | kΩ | VDDIO = 3.3V | 117 |+| GMII Set-Up Time | tIS | 1.2 | | | ns | | 118 |+| GMII Hold Time | tIH | 1.2 | | | ns | | 118 |+| GMII Output Delay Respect to Clock Falling Edge | tOD | | | 1 | ns | | 118 |+| GMII Clock Cycle | | | 8 | | ns | | 118 |+| 100BASE-TX Transmitter 3.3V Analog Current | IDX | | 142 | | mA | VDDAT; all ports 100% utilization | 116 |+| 100BASE-TX 1.2V Current | ID12 | | 35 | | mA | VDD12A + VDD12D; all ports 100% utilization | 116 |+| 100BASE-TX Digital IO 3.3V Current | IDDIO | | 15 | | mA | VDDIO; all ports 100% utilization | 116 |+| 10BASE-T Transmitter 3.3V Analog Current | IDX | | 135 | | mA | VDDAT; all ports 100% utilization | 116 |+| 10BASE-T 1.2V Current | ID12 | | 30 | | mA | VDD12A + VDD12D; all ports 100% utilization | 116 |+| Soft Power-Down Mode 3.3V Current | ISPDM1 | | 0.07 | | mA | VDDAT + VDDIO | 116 |+| Soft Power-Down Mode 1.2V Current | ISPDM2 | | 0.2 | | mA | VDD12A + VDD12D | 116 |+| Energy Detect Mode (EDPD) 3.3V Current | IEDM1 | | 21 | | mA | VDDAT + VDDIO | 116 |+| 100BT EEE Mode at Idle 3.3V Current | IEEE1 | | 22.5 | | mA | VDDAT + VDDIO | 116 |++## CAD (KiCad official)++- Symbol: `KSZ8795CLXCC`+- Footprint: `Package_QFP:LQFP-80_10x10mm_P0.4mm`+- 3D model: LQFP-80(10x10) (KiCad packages3D, STEP)+- 3D model files: `ksz8795clxcc-etched.step` / `ksz8795clxcc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ksz8795clxcc.step` / `ksz8795clxcc.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip Tech datasheet](docs/ksz8795clxcc-datasheet.pdf) (135 pp, sha256 `d02372cc17b71e8b`, retrieved 2026-10-31, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ksz8795clxcc-datasheet.pdf)
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ksz8795clxcc.glbadded⋯ 1 unchanged line ⋯
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pin="SCL_MDC" pad="67"/>+ <connect gate="G$1" pin="SPIQ" pad="66"/>+ <connect gate="G$1" pin="LED1_0" pad="65"/>+ <connect gate="G$1" pin="LED1_1" pad="64"/>+ <connect gate="G$1" pin="LED2_0" pad="63"/>+ <connect gate="G$1" pin="LED2_1" pad="62"/>+ <connect gate="G$1" pin="GNDD@4" pad="61"/>+ <connect gate="G$1" pin="RXD5_7" pad="60"/>+ <connect gate="G$1" pin="RXD5_6" pad="59"/>+ <connect gate="G$1" pin="RXD5_5" pad="58"/>+ <connect gate="G$1" pin="RXD5_4" pad="57"/>+ <connect gate="G$1" pin="PME_N" pad="56"/>+ <connect gate="G$1" pin="REFCLKO" pad="55"/>+ <connect gate="G$1" pin="COL5" pad="54"/>+ <connect gate="G$1" pin="CRS5" pad="53"/>+ <connect gate="G$1" pin="RXER5" pad="52"/>+ <connect gate="G$1" pin="RXDV5/CRSDV5/RXD5_CTL" pad="51"/>+ <connect gate="G$1" pin="RXD5_3" pad="50"/>+ <connect gate="G$1" pin="RXD5_2" pad="49"/>+ <connect gate="G$1" pin="VDDIO@3" pad="48"/>+ <connect gate="G$1" pin="GNDD@5" pad="47"/>+ <connect gate="G$1" pin="RXD5_1" pad="46"/>+ <connect gate="G$1" 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Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of LQFP-80_10x10mm_P0.4mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'LQFP-80_10x10mm_P0.4mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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