component
KSZ8081RNBIA-TR
Public Made by Adomby adom
Microchip Tech Ethernet Transceivers, QFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+276−8@@ -1,13 +1,286 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ksz8081rnbia-tr",+ "title": "KSZ8081RNBIA-TR",+ "brief": "Microchip Tech Ethernet Transceivers, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Microchip Tech Ethernet Transceivers, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "interface", "ksz8081rnbia-tr" ],+ "component": {+ "mpn": "KSZ8081RNBIA-TR",+ "manufacturer": "Microchip Tech",+ "package": "QFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881670615273472",+ "parts": {+ "symbol": "ksz8081rnbia-tr.kicad_sym",+ "footprint": "ksz8081rnbia-tr.kicad_mod",+ "model_3d": "ksz8081rnbia-tr.glb",+ "model_3d_step": "ksz8081rnbia-tr.step",+ "lbr": "ksz8081rnbia-tr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference. Also tied to the exposed paddle on the bottom of the QFN."+ },+ {+ "number": "2",+ "name": "VDD_1.2",+ "type": "power_in",+ "description": "1.2V core VDD supplied by the on-chip regulator. Decouple with 2.2 \u00b5F and 0.1 \u00b5F capacitors to ground."+ },+ {+ "number": "3",+ "name": "VDDA_3.3",+ "type": "power_in",+ "description": "3.3V analog VDD supply for the PHY analog front end."+ },+ {+ "number": "4",+ "name": "RXM",+ "type": "bidirectional",+ "description": "Physical receive/transmit signal, negative differential (media-side twisted pair)."+ },+ {+ "number": "5",+ "name": "RXP",+ "type": "bidirectional",+ "description": "Physical receive/transmit signal, positive differential (media-side twisted pair)."+ },+ {+ "number": "6",+ "name": "TXM",+ "type": "bidirectional",+ "description": "Physical transmit/receive signal, negative differential (media-side twisted pair)."+ },+ {+ "number": "7",+ "name": "TXP",+ "type": "bidirectional",+ "description": "Physical transmit/receive signal, positive differential (media-side twisted pair)."+ },+ {+ "number": "8",+ "name": "XO",+ "type": "output",+ "description": "Crystal feedback for the 25 MHz crystal. Leave no-connect if an oscillator or external clock source is used on XI."+ },+ {+ "number": "9",+ "name": "XI",+ "type": "input",+ "description": "25 MHz mode: 25 MHz \u00b150 ppm crystal, oscillator or external clock input. 50 MHz mode: 50 MHz \u00b150 ppm oscillator or external clock input (REF_CLK pin becomes no-connect in this mode)."+ },+ {+ "number": "10",+ "name": "REXT",+ "type": "input",+ "description": "Sets PHY transmit output current. Connect a 6.49 k\u03a9 resistor to ground on this pin."+ },+ {+ "number": "11",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Management Interface (MII) data I/O. Weak internal pull-up, open-drain output; requires an external 1.0 k\u03a9 pull-up resistor."+ },+ {+ "number": "12",+ "name": "MDC",+ "type": "input",+ "description": "Management Interface (MII) clock input, synchronous to MDIO. Internal pull-up."+ },+ {+ "number": "13",+ "name": "PHYAD0",+ "type": "bidirectional",+ "description": "Strap-in pin: pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. Ipu/O buffer."+ },+ {+ "number": "14",+ "name": "PHYAD1",+ "type": "bidirectional",+ "description": "Strap-in pin: pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. Ipd/O buffer."+ },+ {+ "number": "15",+ "name": "RXD1/PHYAD2",+ "type": "bidirectional",+ "description": "RMII Mode: RMII Receive Data Output[1], synchronous to the 50 MHz REF_CLK. Config Mode: latched as PHYADDR[2] at the de-assertion of reset."+ },+ {+ "number": "16",+ "name": "RXD0/DUPLEX",+ "type": "bidirectional",+ "description": "RMII Mode: RMII Receive Data Output[0], synchronous to the 50 MHz REF_CLK. Config Mode: latched as DUPLEX (pull-up = Half-duplex default, pull-down = Full-duplex) at the de-assertion of reset."+ },+ {+ "number": "17",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O supply: 3.3 V, 2.5 V, or 1.8 V VDD. Sets the digital I/O voltage domain."+ },+ {+ "number": "18",+ "name": "CRS_DV/CONFIG2",+ "type": "bidirectional",+ "description": "RMII Mode: RMII Carrier Sense/Receive Data Valid output. Config Mode: pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset (see CONFIG[2:0] mode table)."+ },+ {+ "number": "19",+ "name": "REF_CLK/B-CAST_OFF",+ "type": "bidirectional",+ "description": "RMII Mode: in 25 MHz mode this pin drives the 50 MHz RMII reference clock output to the MAC; in 50 MHz mode this pin is a no-connect (clock enters via XI). Config Mode: pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset."+ },+ {+ "number": "20",+ "name": "RXER/ISO",+ "type": "bidirectional",+ "description": "RMII Mode: RMII Receive Error output. Config Mode: pull-up/pull-down value is latched as ISOLATE (Pull-up = Enable, Pull-down = Disable default) at the de-assertion of reset."+ },+ {+ "number": "21",+ "name": "INTRP/NAND_Tree#",+ "type": "bidirectional",+ "description": "Programmable Interrupt Output. Weak internal pull-up, open-drain output; requires an external 1.0 k\u03a9 pull-up resistor. Config Mode: pull-up/pull-down value is latched as NAND_Tree# (Pull-up default = Disable, Pull-down = Enable) at the de-assertion of reset."+ },+ {+ "number": "22",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect. Pin is not bonded to the die and can be left floating."+ },+ {+ "number": "23",+ "name": "TXEN",+ "type": "input",+ "description": "RMII Transmit Enable input. When asserted, TXD[1:0] carries valid data from the MAC to the PHY, synchronous to the 50 MHz RMII reference clock."+ },+ {+ "number": "24",+ "name": "TXD0",+ "type": "input",+ "description": "RMII Transmit Data Input[0], synchronous to the 50 MHz RMII reference clock."+ },+ {+ "number": "25",+ "name": "TXD1",+ "type": "input",+ "description": "RMII Transmit Data Input[1], synchronous to the 50 MHz RMII reference clock."+ },+ {+ "number": "26",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect. Pin is not bonded to the die and can be left floating."+ },+ {+ "number": "27",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect. Pin is not bonded to the die and can be left floating."+ },+ {+ "number": "28",+ "name": "CONFIG0",+ "type": "bidirectional",+ "description": "Strap-in pin: pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. Combined with CONFIG1 and CONFIG2 to select interface mode (001 = RMII, 101 = RMII back-to-back on RNB)."+ },+ {+ "number": "29",+ "name": "CONFIG1",+ "type": "bidirectional",+ "description": "Strap-in pin: pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See CONFIG[2:0] mode encoding."+ },+ {+ "number": "30",+ "name": "LED0/NWAYEN",+ "type": "bidirectional",+ "description": "Programmable LED0 output; function is selectable via Register 1Fh bits [5:4] (Link/Activity or Link indication). Config Mode: latched as NWAYEN (Pull-up default = enable auto-negotiation, Pull-down = disable) at the de-assertion of reset."+ },+ {+ "number": "31",+ "name": "LED1/SPEED",+ "type": "bidirectional",+ "description": "Programmable LED1 output; function is selectable via Register 1Fh bits [5:4] (Speed 10/100 or Activity). Config Mode: latched as SPEED (Pull-up default = 100 Mbps, Pull-down = 10 Mbps) at the de-assertion of reset."+ },+ {+ "number": "32",+ "name": "RST#",+ "type": "input",+ "description": "Active-low chip reset input with internal pull-up."+ },+ {+ "number": "PAD",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed paddle ground on the bottom of the QFN package. Must be soldered to the PCB ground plane for electrical and thermal return."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881670615273472",+ "pages": 66,+ "sha256": "773e44836a09f168",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Microchip Tech",+ "Package": "QFN-32-EP(5x5)",+ "Category": "Interface",+ "Pins": "33"+ }+ },+ "variants": [+ {+ "mpn": "KSZ8081RNBIA-TR",+ "kind": "packaging"+ },+ {+ "mpn": "KSZ8081MNX",+ "kind": "unknown"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ksz8081rnbia-tr"+ ],+ "discovery_pitch": "KSZ8081RNBIA-TR (Microchip Tech) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +298,5 @@ "docs/ksz8081rnbia-tr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }