KSZ8081RNACA-TR

@@ -0,0 +1,65 @@+# KSZ8081RNACA-TR++**Microchip** · Ethernet Controllers · QFN-24-EP(4x4)++KSZ8081RNACA-TR from Microchip, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD_1.2 | power_in | 1.2V core VDD supplied by the on-chip regulator. Decouple with 2.2 uF and 0.1 uF capacitors to ground. |+| 2 | VDDA_3.3 | power_in | 3.3V analog VDD supply. |+| 3 | RXM | bidirectional | Physical Receive or Transmit Signal (negative differential). Media-side MDI/MDI-X pair, on-chip terminated. |+| 4 | RXP | bidirectional | Physical Receive or Transmit Signal (positive differential). Media-side MDI/MDI-X pair, on-chip terminated. |+| 5 | TXM | bidirectional | Physical Transmit or Receive Signal (negative differential). Media-side MDI/MDI-X pair, on-chip terminated. |+| 6 | TXP | bidirectional | Physical Transmit or Receive Signal (positive differential). Media-side MDI/MDI-X pair, on-chip terminated. |+| 7 | XO | output | Crystal feedback for 25 MHz crystal. Leave as a no-connect if an oscillator or external clock source is used on XI. |+| 8 | XI | input | 25 MHz +/-50 ppm crystal/oscillator/external clock input (RMII 25 MHz mode). KSZ8081RNA power-up default: 25 MHz crystal on this pin. Programmable to 50 MHz mode via PHY Register 1Fh bit [7]. |+| 9 | REXT | input | PHY transmit output current setting. Connect a 6.49 kOhm 1% resistor from this pin to ground. |+| 10 | MDIO | bidirectional | Management Interface (MII) data I/O. Open-drain with weak internal pull-up; requires an external 1.0 kOhm pull-up resistor. |+| 11 | MDC | input | Management Interface (MII) clock input, synchronous to MDIO. Weak internal pull-up. |+| 12 | RXD1 | output | RMII Receive Data Output[1]. Synchronous to the 50 MHz RMII reference clock; two bits sent per clock while CRS_DV is asserted. Internal pull-down active at reset. |+| 13 | RXD0 | output | RMII Receive Data Output[0]. Synchronous to the 50 MHz RMII reference clock; two bits sent per clock while CRS_DV is asserted. Internal pull-up active at reset. |+| 14 | VDDIO | power_in | Digital I/O supply. Selectable 3.3V, 2.5V, or 1.8V. |+| 15 | CRS_DV/PHYAD[1:0] | bidirectional | RMII mode: Carrier Sense / Receive Data Valid output to the MAC. Config mode: the pull-up/pull-down value on this pin is latched as PHYAD[1:0] at de-assertion of reset (pull-up = 0x3, pull-down default = 0x0). |+| 16 | REF_CLK | bidirectional | RMII 25 MHz mode (RNA default): outputs the 50 MHz RMII reference clock to the MAC. RMII 50 MHz mode: no-connect. Latched pull-down active at reset. |+| 17 | RXER | output | RMII Receive Error output. Needs a latched pull-down at de-assertion of reset for normal operation; add an external pull-down if the MAC drives this pin high. |+| 18 | INTRP | output | Programmable interrupt output. Open-drain with weak internal pull-up; requires an external 1.0 kOhm pull-up resistor. |+| 19 | TXEN | input | RMII Transmit Enable input from the MAC. |+| 20 | TXD0 | input | RMII Transmit Data Input[0] from the MAC. Synchronous to the 50 MHz RMII reference clock while TXEN is asserted. |+| 21 | TXD1 | bidirectional | RMII Transmit Data Input[1] from the MAC. NAND Tree mode: acts as the NAND tree output pin. |+| 22 | GND | power_in | Ground. |+| 23 | LED0/ANEN_SPEED | bidirectional | Programmable LED0 output (Link/Activity by default; modes selected via Register 1Fh bits [5:4]). Config mode: latched at de-assertion of reset as auto-negotiation enable (pull-up default = enabled) and speed select (pull-up = 100 Mbps, pull-down = 10 Mbps). |+| 24 | RST# | input | Chip reset, active-low. Weak internal pull-up. |+| 25 | PADDLE_GND | power_in | Exposed paddle on the bottom of the QFN package. Must be soldered to the board ground plane. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip |+| Package | QFN-24-EP(4x4) |+| Category | Interface |+| Pins | 25 |++## Ordering variants++- `KSZ8081RNACA-TR`+- `KSZ8081RNACA-TRKSZ8081RNDCA-TR`++## CAD (KiCad official)++- Symbol: `KSZ8081RNACA-TR`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip datasheet](docs/ksz8081rnaca-tr-datasheet.pdf) (52 pp, sha256 `6d02bb0e0b96569f`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ksz8081rnaca-tr-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "ksz8081rnaca-tr",+  "version": "0.1.0",+  "type": "component",+  "description": "Microchip Ethernet Controllers, QFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "ksz8081rnaca-tr"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ksz8081rnaca-tr.kicad_sym",+    "ksz8081rnaca-tr.kicad_mod",+    "ksz8081rnaca-tr.glb",+    "ksz8081rnaca-tr.step",+    "ksz8081rnaca-tr.lbr",+    "docs/hero.png",+    "docs/ksz8081rnaca-tr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file