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Initial commit: component/isosd61l

Ray ·06fd5ee626 ·1h ago
2 files changed +300
README.mdadded+52
@@ -0,0 +1,52 @@+# ISOSD61L++**STMicroelectronics** · Isolated ADCs · SOIC-16-300mil++ISOSD61L from STMicroelectronics, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDDISO | power_in | High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V). |+| 2 | VIN+ | power_in | Positive analog input of the sigma-delta modulator; full-scale differential range is ±320 mV, recommended input voltage is -200 mV to 200 mV. |+| 3 | VIN- | power_in | Negative analog input of the sigma-delta modulator; forms a differential pair with VIN+ over the ±320 mV full-scale range. |+| 4 | GNDISO | power_in | Ground for the high-voltage (isolated) side of the device. |+| 5 | NC | unconnected | Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode. |+| 6 | NC | unconnected | Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode. |+| 7 | VDDISO | power_in | High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V). |+| 8 | GNDISO | power_in | Ground for the high-voltage (isolated) side of the device. |+| 9 | GND | power_in | Ground for the low-voltage (digital) side of the device. |+| 10 | MDAT- | output | Negative LVDS serial data output of the 1-bit modulator bitstream (ISOSD61L only; NC on the single-ended ISOSD61). |+| 11 | MDAT+ | output | Positive LVDS serial data output of the 1-bit modulator bitstream, provided two clock cycles after the effective sampling instant with a data delay of 5 to 20 ns after the clock edge. |+| 12 | MCLKIN- | input | Negative LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle (ISOSD61L only; NC on the single-ended ISOSD61). |+| 13 | MCLKIN+ | input | Positive LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle. |+| 14 | VDD | power_in | Low-voltage (digital) side supply; recommended range is 3 V to 5.5 V. |+| 15 | NC | unconnected | Not connected; no function is stated in the datasheet. |+| 16 | GND | power_in | Ground for the low-voltage (digital) side of the device. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SOIC-16-300mil |+| Category | Signal Isolation Devices |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ISOSD61L`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `isosd61l-etched.step` / `isosd61l-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `isosd61l.step` / `isosd61l.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603050776914632705) (23 pp, sha256 `e6ef0e8105c57581`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/isosd61l-datasheet.pdf)
page.jsonadded+248
@@ -0,0 +1,248 @@+{+  "slug": "isosd61l",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics Isolated ADCs, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "signal isolation devices",+    "isosd61l",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "isosd61l.kicad_sym",+    "isosd61l.kicad_mod",+    "isosd61l.glb",+    "isosd61l.step",+    "isosd61l.lbr",+    "docs/hero.png",+    "docs/isosd61l-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "isosd61l-hero.glb",+    "isosd61l-hero.overlay.json"+  ],+  "component": {+    "mpn": "ISOSD61L",+    "manufacturer": "STMicroelectronics",+    "package": "SOIC-16-300mil",+    "pin_count": 16,+    "category": "Signal Isolation Devices",+    "subcategory": "Isolated ADCs",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603050776914632705",+    "parts": {+      "symbol": "isosd61l.kicad_sym",+      "footprint": "isosd61l.kicad_mod",+      "model_3d": "isosd61l-hero.glb",+      "model_3d_plain": "isosd61l.glb",+      "model_3d_step": "isosd61l-etched.step",+      "model_3d_step_plain": "isosd61l.step",+      "lbr": "isosd61l.lbr"+    },+    "distributor_links": {+      "lcsc": "C5269732",+      "digikey": "497-ISOSD61L-ND",+      "mouser": "511-ISOSD61L"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T18:12:59Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "497-ISOSD61L-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "511-ISOSD61L",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "VDDISO",+        "type": "power_in",+        "description": "High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V)."+      },+      {+        "number": "2",+        "name": "VIN+",+        "type": "power_in",+        "description": "Positive analog input of the sigma-delta modulator; full-scale differential range is ±320 mV, recommended input voltage is -200 mV to 200 mV."+      },+      {+        "number": "3",+        "name": "VIN-",+        "type": "power_in",+        "description": "Negative analog input of the sigma-delta modulator; forms a differential pair with VIN+ over the ±320 mV full-scale range."+      },+      {+        "number": "4",+        "name": "GNDISO",+        "type": "power_in",+        "description": "Ground for the high-voltage (isolated) side of the device."+      },+      {+        "number": "5",+        "name": "NC",+        "type": "unconnected",+        "description": "Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode."+      },+      {+        "number": "6",+        "name": "NC",+        "type": "unconnected",+        "description": "Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode."+      },+      {+        "number": "7",+        "name": "VDDISO",+        "type": "power_in",+        "description": "High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V)."+      },+      {+        "number": "8",+        "name": "GNDISO",+        "type": "power_in",+        "description": "Ground for the high-voltage (isolated) side of the device."+      },+      {+        "number": "9",+        "name": "GND",+        "type": "power_in",+        "description": "Ground for the low-voltage (digital) side of the device."+      },+      {+        "number": "10",+        "name": "MDAT-",+        "type": "output",+        "description": "Negative LVDS serial data output of the 1-bit modulator bitstream (ISOSD61L only; NC on the single-ended ISOSD61)."+      },+      {+        "number": "11",+        "name": "MDAT+",+        "type": "output",+        "description": "Positive LVDS serial data output of the 1-bit modulator bitstream, provided two clock cycles after the effective sampling instant with a data delay of 5 to 20 ns after the clock edge."+      },+      {+        "number": "12",+        "name": "MCLKIN-",+        "type": "input",+        "description": "Negative LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle (ISOSD61L only; NC on the single-ended ISOSD61)."+      },+      {+        "number": "13",+        "name": "MCLKIN+",+        "type": "input",+        "description": "Positive LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Low-voltage (digital) side supply; recommended range is 3 V to 5.5 V."+      },+      {+        "number": "15",+        "name": "NC",+        "type": "unconnected",+        "description": "Not connected; no function is stated in the datasheet."+      },+      {+        "number": "16",+        "name": "GND",+        "type": "power_in",+        "description": "Ground for the low-voltage (digital) side of the device."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Pins 5 and 6 are marked NC(1) and the datasheet says they are for test purposes only and must be con; Pin 15 is listed as NC in Table 1 and the pin diagram with no further description or GND requirement; Pin 1 and pin 7 VDDISO, pins 4 and 8 GNDISO, and pins 9 and 16 GND are duplicated pins; each is list"+        ],+        "pages_sent": 23,+        "cost_usd": 0.0746,+        "at": "2026-10-08T18:12:43"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603050776914632705",+        "pages": 23,+        "sha256": "e6ef0e8105c57581",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "isosd61l.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          9.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "isosd61l-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          9.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "177ad56693a2bfe309eb32a0182b8b6c6aac20e50c801b7f7a5a60c46e914d2e",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file