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Set visibility: public

Ray ·1b1c3c62f4 ·1mo ago ·parent 974401f
1 file changed +10−7
page.json+10−7
@@ -32,19 +32,19 @@         "number": "1",         "name": "VCC1",         "type": "power_in",-        "description": "Power supply for side 1 (input for channel B, output for channel A). Operating range 2.25 V to 5.5 V referenced to GND1. Decouple with a low-ESR ceramic capacitor (e.g. 0.1 \u00b5F) close to the pin."+        "description": "Power supply for side 1 (input for channel B, output for channel A). Operating range 2.25 V to 5.5 V referenced to GND1. Decouple with a low-ESR ceramic capacitor (e.g. 0.1 µF) close to the pin."       },       {         "number": "2",         "name": "OUTA",         "type": "output",-        "description": "Digital output of channel A on side 1. Channel A is the reverse channel; this pin mirrors the logic level applied to INA on side 2. Drives push-pull CMOS levels referenced to VCC1/GND1 with IOH up to \u22124 mA at VCC = 5 V."+        "description": "Digital output of channel A on side 1. Channel A is the reverse channel; this pin mirrors the logic level applied to INA on side 2. Drives push-pull CMOS levels referenced to VCC1/GND1 with IOH up to −4 mA at VCC = 5 V."       },       {         "number": "3",         "name": "INB",         "type": "input",-        "description": "Digital input of channel B on side 1. Channel B is the forward channel; the logic level driven here appears at OUTB on side 2. LVCMOS input thresholds referenced to VCC1 (VIH \u2265 0.7\u00b7VCC1, VIL \u2264 0.3\u00b7VCC1). Default output state (no F suffix) is high when input is lost."+        "description": "Digital input of channel B on side 1. Channel B is the forward channel; the logic level driven here appears at OUTB on side 2. LVCMOS input thresholds referenced to VCC1 (VIH ≥ 0.7·VCC1, VIL ≤ 0.3·VCC1). Default output state (no F suffix) is high when input is lost."       },       {         "number": "4",@@ -62,19 +62,19 @@         "number": "6",         "name": "OUTB",         "type": "output",-        "description": "Digital output of channel B on side 2. Mirrors the logic level driven at INB on side 1. Push-pull CMOS output referenced to VCC2/GND2 with IOH up to \u22124 mA at VCC = 5 V."+        "description": "Digital output of channel B on side 2. Mirrors the logic level driven at INB on side 1. Push-pull CMOS output referenced to VCC2/GND2 with IOH up to −4 mA at VCC = 5 V."       },       {         "number": "7",         "name": "INA",         "type": "input",-        "description": "Digital input of channel A on side 2 (reverse channel). Logic level driven here appears at OUTA on side 1. LVCMOS thresholds referenced to VCC2 (VIH \u2265 0.7\u00b7VCC2, VIL \u2264 0.3\u00b7VCC2)."+        "description": "Digital input of channel A on side 2 (reverse channel). Logic level driven here appears at OUTA on side 1. LVCMOS thresholds referenced to VCC2 (VIH ≥ 0.7·VCC2, VIL ≤ 0.3·VCC2)."       },       {         "number": "8",         "name": "VCC2",         "type": "power_in",-        "description": "Power supply for side 2 (input for channel A, output for channel B). Operating range 2.25 V to 5.5 V referenced to GND2. Decouple with a low-ESR ceramic capacitor (e.g. 0.1 \u00b5F) close to the pin."+        "description": "Power supply for side 2 (input for channel A, output for channel B). Operating range 2.25 V to 5.5 V referenced to GND2. Decouple with a low-ESR ceramic capacitor (e.g. 0.1 µF) close to the pin."       }     ],     "provenance": {@@ -138,5 +138,8 @@     "docs/iso7721dwvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file