ISL78301FVEAZ

@@ -0,0 +1,58 @@+# ISL78301FVEAZ++**RENESAS** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-14++ISL78301FVEAZ from RENESAS, in a HTSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 2 | IN | power_in | Input supply pin. Recommended operating range +3V to +40V (absolute max +45V). A minimum 0.1µF ceramic input capacitor is required for proper operation. |+| 3 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 4 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 5 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 6 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 7 | EN | input | Enable input (40V tolerant TTL/CMOS logic). Drive HIGH (VEN_H = 1.485V typ) to enable the regulator; drive LOW (VEN_L = 0.975V typ) to place the device in shutdown mode (~2µA). Absolute max GND-0.3V to VCC; recommended 0V to +40V. Input current ~26nA typ. |+| 8 | GND | power_in | Ground pin. Return for the internal reference, control logic, and output capacitor. Route directly to the ground plane; the exposed pad (EPAD) should also be tied to this GND plane. |+| 9 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 10 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 11 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 12 | ADJ/NC | unconnected | On this 3.3V fixed-output part (FVEAZ) this pin is NOT USED and may be connected to GND. On the adjustable version (FVECZ) the same pin becomes the ADJ feedback input (VADJ = 1.223V typ) driven by an external R1/R2 divider to program VOUT from 2.5V to 12V. |+| 13 | NC | unconnected | No connect. Internally terminated; may be left floating or optionally tied to GND. |+| 14 | OUT | power_out | Regulated output. Fixed 3.3V ±1% on this FVEAZ variant, capable of 150mA. A 10µF ceramic output capacitor is required for stability; ground of COUT should return directly to pin 8 (GND). Internally protected by current limit (175mA min) and thermal shutdown (+165°C typ). |+| 15 | EPAD | power_in | Exposed thermal pad on the underside of the HTSSOP-14 package. Solder to the PCB GND copper plane for effective heat dissipation (θJC = 5°C/W; θJA scales with copper area, ~37°C/W typ). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | RENESAS |+| Package | HTSSOP-14 |+| Category | Power Management (PMIC) |+| Pins | 15 |++## Ordering variants++Same part, different packaging or reel option.++- `ISL78301FVEAZ`+- `ISL78301FVEBZ`+- `ISL78301FVECZ`++## CAD (KiCad official)++- Symbol: `ISL78301FVEAZ`+- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590389994662891520) (None pp, sha256 `d17e0215559a974c`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/isl78301fveaz-datasheet.pdf)

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