IP6808_NF

@@ -0,0 +1,68 @@+# IP6808_NF++**INJOINIC IP6808 NF** · Battery Management · QFN-32-EP(5x5)++IP6808_NF from INJOINIC IP6808 NF, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SENSEP | input | VBUS current positive sense node. Connects to the high side of the VBUS current-sense shunt for input current monitoring/overcurrent protection. |+| 2 | SENSEN | input | VBUS current negative sense node. Connects to the low side of the VBUS current-sense shunt. |+| 3 | DCH_V | input | Power rail voltage detect pin for external PMOS discharge path. May be left floating when the external PMOS is not used. Absolute max 25 V. |+| 4 | DCH_G | output | Gate drive for external discharge PMOS. May be left floating when the external PMOS is not used. |+| 5 | CC1 | bidirectional | USB Type-C CC1 line, also used for firmware upgrade. In Micro-USB applications, connect to the ID line for firmware download. |+| 6 | CC2 | bidirectional | USB Type-C CC2 line, also used for firmware upgrade. |+| 7 | DM | bidirectional | USB D- data line. Absolute max 20 V; recommended operating range up to 5.5 V. |+| 8 | DP | bidirectional | USB D+ data line. Absolute max 20 V; recommended operating range up to 5.5 V. |+| 9 | Vcoil_Sense | input | Coil voltage sense input. Fed by the resistor divider on the transmitter coil for ASK demodulation and coil voltage monitoring. |+| 10 | FB | output | External DCDC voltage control pin. Used to modulate the external DC/DC output voltage in DPM/Dynamic Power Modulation applications. |+| 11 | HG2 | output | H-bridge high-side NMOS gate drive for half-bridge 2. Referenced to LX2 through BST2 bootstrap. |+| 12 | LX2 | passive | H-bridge switching node 2. Connect to the source of the high-side NMOS / drain of the low-side NMOS of half-bridge 2 and to the bootstrap capacitor return. |+| 13 | BST2 | power_in | Bootstrap capacitor node for half-bridge 2. Connect a bootstrap capacitor between BST2 and LX2 to generate the high-side gate drive supply. |+| 14 | LG2 | output | H-bridge low-side NMOS gate drive for half-bridge 2. Referenced to PGND. |+| 15 | HVCC | power_out | Internal 5 V LDO output used as the boost supply for the H-bridge high-side MOSFET gate drivers. Decouple to GND with a capacitor. |+| 16 | LG1 | output | H-bridge low-side NMOS gate drive for half-bridge 1. Referenced to PGND. |+| 17 | BST1 | power_in | Bootstrap capacitor node for half-bridge 1. Connect a bootstrap capacitor between BST1 and LX1 to generate the high-side gate drive supply. |+| 18 | LX1 | passive | H-bridge switching node 1. Connect to the source of the high-side NMOS / drain of the low-side NMOS of half-bridge 1 and to the bootstrap capacitor return. |+| 19 | HG1 | output | H-bridge high-side NMOS gate drive for half-bridge 1. Referenced to LX1 through BST1 bootstrap. |+| 20 | Test1 | bidirectional | Test1 pin. Used together with Test2 for factory firmware upgrade (Method 1). Voltage range GND-0.3 V to VCC+0.3 V. |+| 21 | LED1 | output | LED1 status output. Drives an LED directly through a series current-limit resistor to indicate charging/system state. |+| 22 | DEBUG | bidirectional | Debug pin used for internal test/debug access. |+| 23 | Test2 | bidirectional | Test2 pin. Used together with Test1 for factory firmware upgrade (Method 1). Voltage range GND-0.3 V to VCC+0.3 V. |+| 24 | LED2 | output | LED2 status output. Drives an LED directly through a series current-limit resistor to indicate charging/system state. |+| 25 | NTC_Sense | input | NTC thermistor sense input. Trips thermal shutdown when the divider voltage drops below ~1.0 V; charging resumes when above ~1.3 V. Must be pulled high if unused. |+| 26 | GND | power_in | Analog ground reference for the IC. |+| 27 | Comm_V | input | Voltage-path communication/ASK demodulation input. AC-coupled from the coil voltage divider through a high-pass filter for Qi communication decoding. |+| 28 | Comm_I | input | Current-path communication/ASK demodulation input. AC-coupled from the external current-sense op-amp output for Qi communication decoding. |+| 29 | VDD | power_out | Internal ~1.8 V core supply LDO output. Connect a 1 uF decoupling capacitor to GND; do not drive externally. |+| 30 | VCC | power_out | Internal ~3.15 V IO supply LDO output. Connect a 1 uF decoupling capacitor to GND; do not drive externally. Absolute max 5 V. |+| 31 | VSYS | power_in | System power input for the IC. Recommended operating range 2.9 V to 7.4 V (absolute max 6 V per Abs-Max table - note conflict). |+| 32 | VBUS | power_in | VBUS charge/discharge detect pin. Absolute max 25 V; recommended operating range 4.5 V to 22 V. |+| 33 | EPAD | power_in | Exposed thermal pad / PGND. Must be soldered to the PCB ground plane for power dissipation and to serve as the power ground return. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | INJOINIC IP6808 NF |+| Package | QFN-32-EP(5x5) |+| Category | PMIC |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `IP6808_NF`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [INJOINIC IP6808 NF datasheet](docs/ip6808-nf-datasheet.pdf) (18 pp, sha256 `608311f63e380a62`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ip6808-nf-datasheet.pdf)

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