IP6538-AC

@@ -0,0 +1,76 @@+# IP6538-AC++**INJOINIC** · Battery Management · QFN-32-EP(5x5)++IP6538-AC from INJOINIC, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUT1G | output | Gate drive to control external NMOS on VOUT1 output path (load-switch / plug-detection MOSFET). |+| 2 | VOUT2G | output | Gate drive to control external NMOS on VOUT2 output path (load-switch / plug-detection MOSFET). |+| 3 | VOUT2 | input | VOUT2 output plug-in detection sense pin (senses port-2 downstream voltage for auto plug detection). |+| 4 | NC | unconnected | Floating pin, do not connect. |+| 5 | CCB1 | bidirectional | Type-C port 2 CC1 line (Group B). PD/BMC communication and CC attach detection. Abs max 30V; OVP triggers >6.5V. |+| 6 | CCB2 | bidirectional | Type-C port 2 CC2 line (Group B). PD/BMC communication and CC attach detection. Abs max 30V; OVP triggers >6.5V. |+| 7 | CCA1 | bidirectional | Type-C port 1 CC1 line (Group A). Note: on IP6538-AC VOUT1 is USB Type-A, so CCA pins are typically unused on this variant. Abs max 30V; OVP >6.5V. |+| 8 | CCA2 | bidirectional | Type-C port 1 CC2 line (Group A). See CCA1 note for IP6538-AC. Abs max 30V; OVP >6.5V. |+| 9 | DM2 | bidirectional | VOUT2 USB D- line. Used for BC1.2/Apple/Samsung/QC/FCP/AFC/PE handshake. Abs max 30V; DPDM OVP triggers >4.8V. |+| 10 | DP2 | bidirectional | VOUT2 USB D+ line. Fast-charge protocol handshake. Abs max 30V; DPDM OVP >4.8V. |+| 11 | DP1 | bidirectional | VOUT1 USB D+ line. Fast-charge protocol handshake. Abs max 30V; DPDM OVP >4.8V. |+| 12 | DM1 | bidirectional | VOUT1 USB D- line. Fast-charge protocol handshake. Abs max 30V; DPDM OVP >4.8V. |+| 13 | GND | power_in | Analog / signal ground reference. |+| 14 | VIN | power_in | Buck-converter power input. Operating 8.2V-32V, absolute max 40V. Tie all VIN pins (14,15,26,27) together with local bulk + HF decoupling. |+| 15 | VIN | power_in | Buck-converter power input (parallel with pin 14). Operating 8.2V-32V, absolute max 40V. |+| 16 | HLED | output | Fast-charge state indicator LED drive. Open-drain style drive for a status LED (asserted while fast-charge protocol is active). |+| 17 | NC | unconnected | Floating pin, do not connect. |+| 18 | PGND | power_in | Power ground return for the buck-stage low-side FET. Connect to the ground pour with short, wide copper adjacent to input caps. |+| 19 | LX | power_out | DCDC switch node; connect to buck inductor. Swings from PGND to VIN. Abs max -0.3V to VIN+0.3V. Tie all LX pins (19-23) together. |+| 20 | LX | power_out | DCDC switch node (parallel with pin 19). Connect to inductor. |+| 21 | LX | power_out | DCDC switch node (parallel). Connect to inductor. |+| 22 | LX | power_out | DCDC switch node (parallel). Connect to inductor. |+| 23 | LX | power_out | DCDC switch node (parallel). Connect to inductor. |+| 24 | BST | passive | Bootstrap capacitor node for the high-side NMOS gate driver. Typical 100nF bootstrap cap between BST and LX. |+| 25 | PGND | power_in | Power ground return (parallel with pin 18). |+| 26 | VIN | power_in | Buck-converter power input (parallel with pins 14/15/27). |+| 27 | VIN | power_in | Buck-converter power input (parallel with pins 14/15/26). |+| 28 | NC | unconnected | Floating pin, do not connect. |+| 29 | VOS1 | input | VOUT1 output-current negative-sense pin. Connect across a 10mOhm alloy sense resistor between VOUT and VOS1 to set port-1 current limit and enable line compensation. |+| 30 | VOS2 | input | VOUT2 output-current negative-sense pin. Connect across a 10mOhm alloy sense resistor between VOUT and VOS2 to set port-2 current limit and enable line compensation. |+| 31 | VOUT | input | Shared VOUT1/VOUT2 output-current positive-sense pin. Kelvin-connect to the buck output rail at the high side of the 10mOhm sense resistors. |+| 32 | VOUT1 | input | VOUT1 output plug-in detection pin (senses port-1 downstream voltage for auto plug detection). |+| 33 | EPAD | power_in | Exposed thermal pad on the underside of the QFN. Must be soldered to the ground pour for thermal dissipation and electrical return. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | INJOINIC |+| Package | QFN-32-EP(5x5) |+| Category | PMIC |+| Pins | 33 |++## Ordering variants++Same part, different packaging or reel option.++- `IP6538-AC`+- `IP6538-ACCC`+- `IP6538-ACAA`++## CAD (KiCad official)++- Symbol: `IP6538-AC`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [INJOINIC datasheet](docs/ip6538-ac-datasheet.pdf) (17 pp, sha256 `1654a7432120a048`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ip6538-ac-datasheet.pdf)

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