component
HR911130A
Public Made by Adomby adom
HANRUN(Zhongshan HanRun Elec) Modular/Ethernet Connector (RJ45) Jacks With Magnetics, Through Hole. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.
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README.md+53−1@@ -1,3 +1,55 @@ # HR911130A -HANRUN(Zhongshan HanRun Elec) Modular/Ethernet Connector (RJ45) Jacks With Magnetics, Through Hole. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet.+::adom-verified{src="/adom/hr911130a/render/verification.json"}++**HANRUN(Zhongshan HanRun Elec)** · Modular/Ethernet Connector (RJ45) Jacks With Magnetics · Through Hole++HR911130A from HANRUN(Zhongshan HanRun Elec), in a Through Hole. Symbol, footprint and 3D model are the ones used on Adom board designs (3D model extracted from the board STEP export, seated in the footprint frame). Pin functions are extracted from the manufacturer datasheet with page references. **Staged for validation: see the open items in the verification log above.**++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CT | passive | _not yet described_ |+| 2 | MDI0+ | passive | Chip-side pin P2 — MDI pair 0 positive (BI_DA+). Connects to the center-tapped primary of the first 1CT:1CT transformer; routes to UTP pin J1 (A+). Terminate to the PHY's TX/RX pair 0 positive. [datasheet p.1] |+| 3 | MDI0- | passive | Chip-side pin P3 — MDI pair 0 negative (BI_DA-). Second lead of pair 0 primary; routes to UTP pin J2 (A-). [datasheet p.1] |+| 4 | MDI1+ | passive | Chip-side pin P4 — MDI pair 1 positive (BI_DB+). Primary lead of the second 1CT:1CT transformer; routes to UTP pin J3 (B+). [datasheet p.1] |+| 5 | MDI2+ | passive | Chip-side pin P5 — MDI pair 2 positive (BI_DC+). Primary lead of the third 1CT:1CT transformer; routes to UTP pin J5 (C-). Note: UTP pin assignment follows the datasheet schematic. [datasheet p.1] |+| 6 | MDI2- | passive | Chip-side pin P6 — MDI pair 2 negative (BI_DC-). Second primary lead of pair 2 transformer; routes to UTP pin J6 (B-). [datasheet p.1] |+| 7 | MDI1- | passive | Chip-side pin P7 — MDI pair 1 negative (BI_DB-). Second primary lead of pair 1 transformer; routes to UTP pin J4 (C+). [datasheet p.1] |+| 8 | MDI3+ | passive | Chip-side pin P8 — MDI pair 3 positive (BI_DD+). Primary lead of the fourth 1CT:1CT transformer; routes to UTP pin J7 (D+). [datasheet p.1] |+| 9 | MDI3- | passive | Chip-side pin P9 — MDI pair 3 negative (BI_DD-). Second primary lead of pair 3 transformer; routes to UTP pin J8 (D-). [datasheet p.1] |+| 10 | BS_COM | passive | _not yet described_ |+| 11 | - | passive | Green LED anode (left LED). Forward voltage 1.8V (min) / 2.8V (max), 20mA, 568nm wavelength. Drive via a current-limiting resistor from the PHY's LED output or Vcc with the cathode (pin 12) sinking to the PHY. [datasheet p.1] |+| 12 | - | passive | Green LED cathode (left LED). Pair with pin 11; typically driven by an open-drain PHY LED output. [datasheet p.1] |+| 13 | - | passive | Yellow LED cathode (right LED). Pair with pin 14; typically driven by an open-drain PHY LED output. [datasheet p.1] |+| 14 | - | passive | Yellow LED anode (right LED). Forward voltage 1.8V (min) / 2.8V (max), 20mA, 585nm wavelength. Drive via a current-limiting resistor from the PHY's LED output or Vcc. [datasheet p.1] |+| S1 | SHIELD | passive | Shield / mounting contact (mechanical); connect per the board design. [from symbol] |+| S2 | SHIELD | passive | Shield / mounting contact (mechanical); connect per the board design. [from symbol] |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HANRUN(Zhongshan HanRun Elec) |+| Package | Through Hole |+| Category | Connectors |+| Pins | 16 |+| LCSC | C54408 |+| Distributor summary (LCSC listing, not datasheet) | 0℃~+70℃ 1 Gold Non-PoE Phosphor bronze RJ45 Jack Right Angle Shielded With Cross Pin With LED 插件 Ethernet Connectors / Modular Connectors (RJ45 RJ11) ROHS |++## CAD++- Symbol: `hr911130a` (source library `RJ45_CDT:HR911130A`)+- Footprint: `RJ45_CDT:HANRUN_HR911130A_RJ45`+- 3D model path in footprint: `${KIPRJMOD}/hr911130a.step`+- 3D files: `hr911130a.step` / `hr911130a.glb`.+- EAGLE/Fusion library: `hr911130a.lbr` (adom-lbr)++## Provenance++- **Datasheet:** [HANRUN(Zhongshan HanRun Elec) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887489490112512) (sha256 `b54a098fdd21c20b`, retrieved 2026-10-08, tier: lcsc)+- **CAD:** Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export.+- **Pins:** KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7).++[Datasheet PDF](docs/hr911130a-datasheet.pdf)
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docs/hr911130a-datasheet.pdfadded⋯ 1 unchanged line ⋯
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hr911130a.lbradded+183@@ -0,0 +1,183 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE eagle SYSTEM "eagle.dtd">+<eagle version="9.6.2">+<drawing>+<settings><setting alwaysvectorfont="no"/></settings>+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>+<layers>+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" 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<gates>+ <gate name="G$1" symbol="HR911130A" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="HR911130A">+ <connects>+ <connect gate="G$1" pin="11" pad="11"/>+ <connect gate="G$1" pin="12" pad="12"/>+ <connect gate="G$1" pin="13" pad="13"/>+ <connect gate="G$1" pin="14" pad="14"/>+ <connect gate="G$1" pin="SHIELD" pad="S1"/>+ <connect gate="G$1" pin="SHIELD@2" pad="S2"/>+ <connect gate="G$1" pin="CT" pad="1"/>+ <connect gate="G$1" pin="MDI0+" pad="2"/>+ <connect gate="G$1" pin="MDI0-" pad="3"/>+ <connect gate="G$1" pin="MDI1+" pad="4"/>+ <connect gate="G$1" pin="MDI2+" pad="5"/>+ <connect gate="G$1" pin="MDI2-" pad="6"/>+ <connect gate="G$1" pin="MDI1-" pad="7"/>+ <connect gate="G$1" pin="MDI3+" pad="8"/>+ <connect gate="G$1" pin="MDI3-" pad="9"/>+ <connect gate="G$1" pin="BS_COM" pad="10"/>+ </connects>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="HR911130A" constant="no"/>+ <attribute name="MANUFACTURER" value="HANRUN(Zhongshan HanRun Elec)" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887489490112512" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/hr911130a" constant="no"/>+ <attribute name="LCSC_PN" value="C54408" constant="no"/>+ </technology>+ </technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
package.jsonadded+202@@ -0,0 +1,202 @@+{+ "slug": "hr911130a",+ "version": "0.1.0",+ "type": "component",+ "tags": [+ "component",+ "connectors",+ "hr911130a",+ "board-derived",+ "staged-for-validation"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "verification.json",+ "hr911130a.kicad_sym",+ "hr911130a.kicad_mod",+ "hr911130a.glb",+ "hr911130a.step",+ "hr911130a.lbr",+ "docs/hero.png",+ "docs/hr911130a-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "HR911130A",+ "manufacturer": "HANRUN(Zhongshan HanRun Elec)",+ "package": "Through Hole",+ "pin_count": 16,+ "category": "Connectors",+ "subcategory": "Modular/Ethernet Connector (RJ45) Jacks With Magnetics",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887489490112512",+ "parts": {+ "symbol": "hr911130a.kicad_sym",+ "footprint": "hr911130a.kicad_mod",+ "model_3d": "hr911130a.glb",+ "model_3d_plain": "hr911130a.glb",+ "model_3d_step": "hr911130a.step",+ "model_3d_step_plain": "hr911130a.step",+ "lbr": "hr911130a.lbr"+ },+ "distributor_links": {+ "digikey": false,+ "digikey_note": "2026-10-08: no exact-MPN listing for HR911130A found via the digikey API.",+ "mouser": false,+ "mouser_note": "2026-10-08: no exact-MPN listing for HR911130A found via the mouser API.",+ "lcsc": {+ "part": "C54408",+ "url": "https://www.lcsc.com/product-detail/C54408.html"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CT",+ "type": "passive",+ "description": ""+ },+ {+ "number": "2",+ "name": "MDI0+",+ "type": "passive",+ "description": "Chip-side pin P2 — MDI pair 0 positive (BI_DA+). Connects to the center-tapped primary of the first 1CT:1CT transformer; routes to UTP pin J1 (A+). Terminate to the PHY's TX/RX pair 0 positive. [datasheet p.1]"+ },+ {+ "number": "3",+ "name": "MDI0-",+ "type": "passive",+ "description": "Chip-side pin P3 — MDI pair 0 negative (BI_DA-). Second lead of pair 0 primary; routes to UTP pin J2 (A-). [datasheet p.1]"+ },+ {+ "number": "4",+ "name": "MDI1+",+ "type": "passive",+ "description": "Chip-side pin P4 — MDI pair 1 positive (BI_DB+). Primary lead of the second 1CT:1CT transformer; routes to UTP pin J3 (B+). [datasheet p.1]"+ },+ {+ "number": "5",+ "name": "MDI2+",+ "type": "passive",+ "description": "Chip-side pin P5 — MDI pair 2 positive (BI_DC+). Primary lead of the third 1CT:1CT transformer; routes to UTP pin J5 (C-). Note: UTP pin assignment follows the datasheet schematic. [datasheet p.1]"+ },+ {+ "number": "6",+ "name": "MDI2-",+ "type": "passive",+ "description": "Chip-side pin P6 — MDI pair 2 negative (BI_DC-). Second primary lead of pair 2 transformer; routes to UTP pin J6 (B-). [datasheet p.1]"+ },+ {+ "number": "7",+ "name": "MDI1-",+ "type": "passive",+ "description": "Chip-side pin P7 — MDI pair 1 negative (BI_DB-). Second primary lead of pair 1 transformer; routes to UTP pin J4 (C+). [datasheet p.1]"+ },+ {+ "number": "8",+ "name": "MDI3+",+ "type": "passive",+ "description": "Chip-side pin P8 — MDI pair 3 positive (BI_DD+). Primary lead of the fourth 1CT:1CT transformer; routes to UTP pin J7 (D+). [datasheet p.1]"+ },+ {+ "number": "9",+ "name": "MDI3-",+ "type": "passive",+ "description": "Chip-side pin P9 — MDI pair 3 negative (BI_DD-). Second primary lead of pair 3 transformer; routes to UTP pin J8 (D-). [datasheet p.1]"+ },+ {+ "number": "10",+ "name": "BS_COM",+ "type": "passive",+ "description": ""+ },+ {+ "number": "11",+ "name": "",+ "type": "passive",+ "description": "Green LED anode (left LED). Forward voltage 1.8V (min) / 2.8V (max), 20mA, 568nm wavelength. Drive via a current-limiting resistor from the PHY's LED output or Vcc with the cathode (pin 12) sinking to the PHY. [datasheet p.1]"+ },+ {+ "number": "12",+ "name": "",+ "type": "passive",+ "description": "Green LED cathode (left LED). Pair with pin 11; typically driven by an open-drain PHY LED output. [datasheet p.1]"+ },+ {+ "number": "13",+ "name": "",+ "type": "passive",+ "description": "Yellow LED cathode (right LED). Pair with pin 14; typically driven by an open-drain PHY LED output. [datasheet p.1]"+ },+ {+ "number": "14",+ "name": "",+ "type": "passive",+ "description": "Yellow LED anode (right LED). Forward voltage 1.8V (min) / 2.8V (max), 20mA, 585nm wavelength. Drive via a current-limiting resistor from the PHY's LED output or Vcc. [datasheet p.1]"+ },+ {+ "number": "S1",+ "name": "SHIELD",+ "type": "passive",+ "description": "Shield / mounting contact (mechanical); connect per the board design. [from symbol]"+ },+ {+ "number": "S2",+ "name": "SHIELD",+ "type": "passive",+ "description": "Shield / mounting contact (mechanical); connect per the board design. [from symbol]"+ }+ ],+ "provenance": {+ "factory_chain": {+ "pipeline": "adom-parts (board-derived) 0.1",+ "pins": "KiCad symbol from the source board + adom-ds2sf datasheet extraction (claude-opus-4-7)",+ "at": "2026-10-08"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588887489490112512",+ "pages": 2,+ "sha256": "b54a098fdd21c20b07ef95727b6872a9f20308cd3804dd975182b6c7e2eb87e6",+ "source_tier": "lcsc"+ },+ "cad": "Footprint, symbol and 3D model as used on Adom board designs; the 3D model was extracted from the board STEP export",+ "pins": {+ "total": 16,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "hr911130a.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin",+ "seat": "z = 0 (PCB top surface)",+ "extents_mm": [+ 16.04,+ 21.3,+ 16.55+ ],+ "zmin_mm": -3.05,+ "footprint_binding": "identity",+ "sha256": "8fded961582456618c38d3dfa20a74991c7366606143282ce5cb6f50a8722886",+ "checked": "2026-10-08",+ "checked_by": "adom-parts/partstep.py (placement inverse from the source board; centroid-matched to KiCad library models on 59 reference cases)"+ }+ ]+ },+ "description": "HANRUN(Zhongshan HanRun Elec) Modular/Ethernet Connector (RJ45) Jacks With Magnetics, Through Hole. KiCad symbol, footprint and 3D as used on Adom boards; pin functions from the manufacturer datasheet."+}
verification.jsonadded+127@@ -0,0 +1,127 @@+{+ "schema": "adom/verification@1",+ "part": "HR911130A",+ "variants": [],+ "entries": [+ {+ "date": "2026-10-08",+ "by": {+ "name": "Claude (AI build)",+ "handle": "claude"+ },+ "status": "open",+ "title": "Automated build checks (awaiting human validation)",+ "scope": [+ "symbol",+ "footprint",+ "3d",+ "pins"+ ],+ "variants": [+ "*"+ ],+ "checks": [+ {+ "text": "Footprint extracted pad-for-pad from the source board and normalized to the footprint frame (back-side parts un-mirrored)",+ "result": "pass"+ },+ {+ "text": "3D model seated z=0 at footprint origin (placement inverse; method centroid-matched to KiCad library models on 59 cases)",+ "result": "pass"+ },+ {+ "text": "adom-lbr generate + lint passed",+ "result": "pass"+ },+ {+ "text": "14 of 16 pins described from the datasheet (adom-ds2sf, page-cited)",+ "result": "note"+ },+ {+ "text": "Not yet checked by a person: land pattern vs datasheet, pin-1/orientation, 3D body vs drawing",+ "result": "note"+ }+ ],+ "evidence": [+ {+ "label": "datasheet",+ "href": "docs/hr911130a-datasheet.pdf"+ }+ ],+ "files": {+ "hr911130a.kicad_sym": "0ac119b1ae0656704dd80ee82e7d539b60b5b5917d5775473227559390c87f20",+ "hr911130a.kicad_mod": "ef6edeb2ef490dca592e62b2cc5fe77fba508d7a41e1461db9b74fa12e629476",+ "hr911130a.step": "8fded961582456618c38d3dfa20a74991c7366606143282ce5cb6f50a8722886"+ }+ },+ {+ "date": "2026-10-08",+ "by": {+ "name": "Claude (AI build)",+ "handle": "claude"+ },+ "status": "open",+ "title": "2 of 16 pins have no datasheet description yet (pins 1, 10).",+ "scope": [+ "review"+ ],+ "variants": [+ "*"+ ],+ "checks": [+ {+ "text": "2 of 16 pins have no datasheet description yet (pins 1, 10).",+ "result": "note"+ }+ ],+ "evidence": [],+ "files": {}+ },+ {+ "date": "2026-10-08",+ "by": {+ "name": "Claude (AI build)",+ "handle": "claude"+ },+ "status": "open",+ "title": "Pin names differ between the board symbol and the datasheet (often equivalent naming; chec...",+ "scope": [+ "review"+ ],+ "variants": [+ "*"+ ],+ "checks": [+ {+ "text": "Pin names differ between the board symbol and the datasheet (often equivalent naming; check): 1: symbol \"CT\" vs datasheet \"P1\"; 10: symbol \"BS_COM\" vs datasheet \"P10\"",+ "result": "note"+ }+ ],+ "evidence": [],+ "files": {}+ },+ {+ "date": "2026-10-08",+ "by": {+ "name": "Claude (AI build)",+ "handle": "claude"+ },+ "status": "open",+ "title": "Datasheet pins not matched to a symbol pin: P1, P10",+ "scope": [+ "review"+ ],+ "variants": [+ "*"+ ],+ "checks": [+ {+ "text": "Datasheet pins not matched to a symbol pin: P1, P10",+ "result": "note"+ }+ ],+ "evidence": [],+ "files": {}+ }+ ]+}