HEF4081BT

@@ -0,0 +1,53 @@+# HEF4081BT++**Nexperia** · Gates · SOIC-14++HEF4081BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Gate 1 input A. CMOS logic input; VIH ≥ 3.5 V @ VDD=5 V, VIL ≤ 1.5 V @ VDD=5 V. Input leakage ±0.1 µA typ. Unused inputs must be tied to VDD or VSS. |+| 2 | 1B | input | Gate 1 input B. CMOS logic input; same electrical characteristics as 1A. Unused inputs must be tied to VDD or VSS. |+| 3 | 1Y | output | Gate 1 output; 1Y = 1A AND 1B. Fully buffered CMOS output, VOH ≥ 4.95 V and VOL ≤ 0.05 V @ VDD=5 V with |IO|<1 µA. |+| 4 | 2Y | output | Gate 2 output; 2Y = 2A AND 2B. Fully buffered CMOS output with standardized symmetrical drive. |+| 5 | 2A | input | Gate 2 input A. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 6 | 2B | input | Gate 2 input B. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 7 | VSS | power_in | Ground reference (0 V). All voltages in the datasheet are referenced to VSS. |+| 8 | 3A | input | Gate 3 input A. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 9 | 3B | input | Gate 3 input B. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 10 | 3Y | output | Gate 3 output; 3Y = 3A AND 3B. Fully buffered CMOS output. |+| 11 | 4Y | output | Gate 4 output; 4Y = 4A AND 4B. Fully buffered CMOS output. |+| 12 | 4A | input | Gate 4 input A. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 13 | 4B | input | Gate 4 input B. CMOS logic input; unused inputs must be tied to VDD or VSS. |+| 14 | VDD | power_in | Positive supply voltage. Recommended operating range 3 V to 15 V; absolute max 18 V. Typical supply current IDD ≤ 1 µA @ VDD=15 V for static inputs. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `HEF4081BTT`++## CAD (KiCad official)++- Symbol: `HEF4081BT`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/HEF4081BT.pdf) (11 pp, sha256 `98a345e3e99a74a2`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hef4081bt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "hef4081bt",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "hef4081bt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hef4081bt.kicad_sym",+    "hef4081bt.kicad_mod",+    "hef4081bt.glb",+    "hef4081bt.step",+    "hef4081bt.lbr",+    "docs/hero.png",+    "docs/hef4081bt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file