HEF4053BT

@@ -0,0 +1,56 @@+# HEF4053BT++**Nexperia** · Analog Switches, Multiplexers · SOIC-16++HEF4053BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 2Y1 | bidirectional | Switch 2 independent input/output Y1. Analog signal path to/from 2Z when S2 = HIGH and E = LOW. Signal range VEE to VDD. |+| 2 | 2Y0 | bidirectional | Switch 2 independent input/output Y0. Analog signal path to/from 2Z when S2 = LOW and E = LOW. Signal range VEE to VDD. |+| 3 | 3Y1 | bidirectional | Switch 3 independent input/output Y1. Analog signal path to/from 3Z when S3 = HIGH and E = LOW. Signal range VEE to VDD. |+| 4 | 3Z | bidirectional | Switch 3 common input/output Z. Analog common terminal of the third SPDT switch. Signal range VEE to VDD. |+| 5 | 3Y0 | bidirectional | Switch 3 independent input/output Y0. Analog signal path to/from 3Z when S3 = LOW and E = LOW. Signal range VEE to VDD. |+| 6 | E | input | Enable input, active LOW. When E = LOW the selected channel in each switch is ON; when E = HIGH all switches are OFF. Digital logic level referenced to VSS (VDD). |+| 7 | VEE | power_in | Negative analog supply voltage. Sets the lower end of the analog signal range. May be tied to VSS for single-supply operation, or driven below VSS (down to -18 V vs VDD) for split-supply level shifting. |+| 8 | VSS | power_in | Ground / digital supply return. Reference (0 V) for the digital logic (Sn, E) and typically for the lower analog rail. |+| 9 | S3 | input | Digital select input for switch 3. LOW routes 3Y0 to 3Z; HIGH routes 3Y1 to 3Z (with E = LOW). |+| 10 | S2 | input | Digital select input for switch 2. LOW routes 2Y0 to 2Z; HIGH routes 2Y1 to 2Z (with E = LOW). |+| 11 | S1 | input | Digital select input for switch 1. LOW routes 1Y0 to 1Z; HIGH routes 1Y1 to 1Z (with E = LOW). |+| 12 | 1Y0 | bidirectional | Switch 1 independent input/output Y0. Analog signal path to/from 1Z when S1 = LOW and E = LOW. Signal range VEE to VDD. |+| 13 | 1Y1 | bidirectional | Switch 1 independent input/output Y1. Analog signal path to/from 1Z when S1 = HIGH and E = LOW. Signal range VEE to VDD. |+| 14 | 1Z | bidirectional | Switch 1 common input/output Z. Analog common terminal of the first SPDT switch. Signal range VEE to VDD. |+| 15 | 2Z | bidirectional | Switch 2 common input/output Z. Analog common terminal of the second SPDT switch. Signal range VEE to VDD. |+| 16 | VDD | power_in | Positive supply voltage. Recommended operating range 3 V to 15 V referenced to VSS; absolute maximum 18 V. Also sets the upper end of the analog signal range and the digital logic HIGH level. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Interface |+| Pins | 16 |++## Ordering variants++- `HEF4053BTT`+- `HEF4053BTTT`++## CAD (KiCad official)++- Symbol: `HEF4053BT`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/HEF4053BT.pdf) (16 pp, sha256 `b87534e2e0345fdb`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hef4053bt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "hef4053bt",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Analog Switches, Multiplexers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "hef4053bt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hef4053bt.kicad_sym",+    "hef4053bt.kicad_mod",+    "hef4053bt.glb",+    "hef4053bt.step",+    "hef4053bt.lbr",+    "docs/hero.png",+    "docs/hef4053bt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file