HEF4040BT

@@ -0,0 +1,57 @@+# HEF4040BT++**Nexperia** · Counters / Dividers · SOIC-16++HEF4040BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q11 | output | Parallel output bit 11 (highest stage, MSB of the 12-stage ripple counter). CMOS push-pull output; toggles every 4096 CP falling edges. |+| 2 | Q5 | output | Parallel output bit 5 of the ripple counter. CMOS push-pull output; toggles every 64 CP falling edges. |+| 3 | Q4 | output | Parallel output bit 4 of the ripple counter. CMOS push-pull output; toggles every 32 CP falling edges. |+| 4 | Q6 | output | Parallel output bit 6 of the ripple counter. CMOS push-pull output; toggles every 128 CP falling edges. |+| 5 | Q3 | output | Parallel output bit 3 of the ripple counter. CMOS push-pull output; toggles every 16 CP falling edges. |+| 6 | Q2 | output | Parallel output bit 2 of the ripple counter. CMOS push-pull output; toggles every 8 CP falling edges. |+| 7 | Q1 | output | Parallel output bit 1 of the ripple counter. CMOS push-pull output; toggles every 4 CP falling edges. |+| 8 | VSS | power_in | Ground supply voltage (0 V reference). |+| 9 | Q0 | output | Parallel output bit 0 (LSB of the 12-stage ripple counter). CMOS push-pull output; toggles on every HIGH-to-LOW transition of CP. |+| 10 | CP | input | Clock input (HIGH-to-LOW edge-triggered). The counter advances by one on each falling edge of CP. |+| 11 | MR | input | Master reset input, active HIGH. A HIGH on MR asynchronously clears all counter stages and forces all outputs Q0-Q11 LOW, independent of CP. |+| 12 | Q8 | output | Parallel output bit 8 of the ripple counter. CMOS push-pull output; toggles every 512 CP falling edges. |+| 13 | Q7 | output | Parallel output bit 7 of the ripple counter. CMOS push-pull output; toggles every 256 CP falling edges. |+| 14 | Q9 | output | Parallel output bit 9 of the ripple counter. CMOS push-pull output; toggles every 1024 CP falling edges. |+| 15 | Q10 | output | Parallel output bit 10 of the ripple counter. CMOS push-pull output; toggles every 2048 CP falling edges. |+| 16 | VDD | power_in | Positive supply voltage. Recommended operating range 3.0 V to 15.0 V; absolute maximum 18 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `HEF4040BTT`++## CAD (KiCad official)++- Symbol: `HEF4040BT`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/HEF4040BT.pdf) (11 pp, sha256 `79a6d15b3b191c5c`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hef4040bt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "hef4040bt",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Counters / Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "hef4040bt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hef4040bt.kicad_sym",+    "hef4040bt.kicad_mod",+    "hef4040bt.glb",+    "hef4040bt.step",+    "hef4040bt.lbr",+    "docs/hero.png",+    "docs/hef4040bt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file