HEF4011BT

@@ -0,0 +1,53 @@+# HEF4011BT++**Nexperia** · Gates · SOIC-14++HEF4011BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Gate 1 input A. CMOS logic input; VIH >= 3.5 V (VDD=5 V), VIL <= 1.5 V (VDD=5 V). Input leakage +/-0.1 uA typ; input capacitance ~7.5 pF. Unused inputs must be tied to VDD or VSS. |+| 2 | 1B | input | Gate 1 input B. CMOS logic input paired with 1A into NAND gate 1. Unused inputs must be tied to VDD or VSS. |+| 3 | 1Y | output | Gate 1 output (NAND of 1A, 1B). Buffered CMOS push-pull output; VOH >= VDD-0.05 V, VOL <= 0.05 V at |IO| < 1 uA. IOH ~ -1.4 mA at VDD=5 V, VO=2.5 V. |+| 4 | 2Y | output | Gate 2 output (NAND of 2A, 2B). Buffered CMOS push-pull output; same drive characteristics as 1Y. |+| 5 | 2A | input | Gate 2 input A. CMOS logic input into NAND gate 2. Unused inputs must be tied to VDD or VSS. |+| 6 | 2B | input | Gate 2 input B. CMOS logic input paired with 2A into NAND gate 2. Unused inputs must be tied to VDD or VSS. |+| 7 | VSS | power_in | Ground reference (0 V). All input/output voltages are referenced to this pin. |+| 8 | 3A | input | Gate 3 input A. CMOS logic input into NAND gate 3. Unused inputs must be tied to VDD or VSS. |+| 9 | 3B | input | Gate 3 input B. CMOS logic input paired with 3A into NAND gate 3. Unused inputs must be tied to VDD or VSS. |+| 10 | 3Y | output | Gate 3 output (NAND of 3A, 3B). Buffered CMOS push-pull output; same drive characteristics as the other Y outputs. |+| 11 | 4Y | output | Gate 4 output (NAND of 4A, 4B). Buffered CMOS push-pull output; same drive characteristics as the other Y outputs. |+| 12 | 4A | input | Gate 4 input A. CMOS logic input into NAND gate 4. Unused inputs must be tied to VDD or VSS. |+| 13 | 4B | input | Gate 4 input B. CMOS logic input paired with 4A into NAND gate 4. Unused inputs must be tied to VDD or VSS. |+| 14 | VDD | power_in | Positive supply voltage. Recommended operating range 3 V to 15 V referenced to VSS; absolute maximum +18 V. Supply current IDD < 30 uA over full temperature range. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `HEF4011BTBT`++## CAD (KiCad official)++- Symbol: `HEF4011BT`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/HEF4011BT.pdf) (11 pp, sha256 `5a28d3c107485298`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hef4011bt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "hef4011bt",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "hef4011bt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hef4011bt.kicad_sym",+    "hef4011bt.kicad_mod",+    "hef4011bt.glb",+    "hef4011bt.step",+    "hef4011bt.lbr",+    "docs/hero.png",+    "docs/hef4011bt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file