component
HEF4011BT
Public Made by Adomby adom
Nexperia Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+152−8@@ -1,13 +1,162 @@ {+ "schema_version": 1,+ "type": "component", "slug": "hef4011bt",+ "title": "HEF4011BT",+ "brief": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "hef4011bt" ],+ "component": {+ "mpn": "HEF4011BT",+ "manufacturer": "Nexperia",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/HEF4011BT.pdf",+ "parts": {+ "symbol": "hef4011bt.kicad_sym",+ "footprint": "hef4011bt.kicad_mod",+ "model_3d": "hef4011bt.glb",+ "model_3d_step": "hef4011bt.step",+ "lbr": "hef4011bt.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Gate 1 input A. CMOS logic input; VIH >= 3.5 V (VDD=5 V), VIL <= 1.5 V (VDD=5 V). Input leakage +/-0.1 uA typ; input capacitance ~7.5 pF. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Gate 1 input B. CMOS logic input paired with 1A into NAND gate 1. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Gate 1 output (NAND of 1A, 1B). Buffered CMOS push-pull output; VOH >= VDD-0.05 V, VOL <= 0.05 V at |IO| < 1 uA. IOH ~ -1.4 mA at VDD=5 V, VO=2.5 V."+ },+ {+ "number": "4",+ "name": "2Y",+ "type": "output",+ "description": "Gate 2 output (NAND of 2A, 2B). Buffered CMOS push-pull output; same drive characteristics as 1Y."+ },+ {+ "number": "5",+ "name": "2A",+ "type": "input",+ "description": "Gate 2 input A. CMOS logic input into NAND gate 2. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "6",+ "name": "2B",+ "type": "input",+ "description": "Gate 2 input B. CMOS logic input paired with 2A into NAND gate 2. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference (0 V). All input/output voltages are referenced to this pin."+ },+ {+ "number": "8",+ "name": "3A",+ "type": "input",+ "description": "Gate 3 input A. CMOS logic input into NAND gate 3. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "9",+ "name": "3B",+ "type": "input",+ "description": "Gate 3 input B. CMOS logic input paired with 3A into NAND gate 3. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "10",+ "name": "3Y",+ "type": "output",+ "description": "Gate 3 output (NAND of 3A, 3B). Buffered CMOS push-pull output; same drive characteristics as the other Y outputs."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Gate 4 output (NAND of 4A, 4B). Buffered CMOS push-pull output; same drive characteristics as the other Y outputs."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Gate 4 input A. CMOS logic input into NAND gate 4. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Gate 4 input B. CMOS logic input paired with 4A into NAND gate 4. Unused inputs must be tied to VDD or VSS."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage. Recommended operating range 3 V to 15 V referenced to VSS; absolute maximum +18 V. Supply current IDD < 30 uA over full temperature range."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/HEF4011BT.pdf",+ "pages": 11,+ "sha256": "5a28d3c107485298",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "SOIC-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "hef4011bt"+ ],+ "discovery_pitch": "HEF4011BT (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +174,5 @@ "docs/hef4011bt-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }