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Initial commit: component/hcf4070ym013tr

Ray ·b0b8fd27e1 ·4d ago
2 files changed +242
README.mdadded+50
@@ -0,0 +1,50 @@+# HCF4070YM013TR++**STMicroelectronics** · Logic Gates · SOIC-14++HCF4070YM013TR from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A for XOR gate 1, accepts 0 to VDD V |+| 2 | B | input | Input B for XOR gate 1, accepts 0 to VDD V |+| 3 | J | output | Output from XOR gate 1, provides 0 to VDD V |+| 4 | K | output | Output from XOR gate 2, provides 0 to VDD V |+| 5 | C | input | Input C for XOR gate 2, accepts 0 to VDD V |+| 6 | D | input | Input D for XOR gate 2, accepts 0 to VDD V |+| 7 | VSS | power_in | Ground (negative supply voltage), 0 V reference |+| 8 | E | input | Input E for XOR gate 3, accepts 0 to VDD V |+| 9 | F | input | Input F for XOR gate 3, accepts 0 to VDD V |+| 10 | L | output | Output from XOR gate 3, provides 0 to VDD V |+| 11 | M | output | Output from XOR gate 4, provides 0 to VDD V |+| 12 | G | input | Input G for XOR gate 4, accepts 0 to VDD V |+| 13 | H | input | Input H for XOR gate 4, accepts 0 to VDD V |+| 14 | VDD | power_in | Positive supply voltage, 3 to 20 V nominal |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `HCF4070YM013TR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `hcf4070ym013tr-etched.step` / `hcf4070ym013tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hcf4070ym013tr.step` / `hcf4070ym013tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/hcf4070ym013tr.pdf) (12 pp, sha256 `0a47eb12ec052f7d`, retrieved 2026-10-01, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hcf4070ym013tr-datasheet.pdf)
page.jsonadded+192
@@ -0,0 +1,192 @@+{+  "slug": "hcf4070ym013tr",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "hcf4070ym013tr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hcf4070ym013tr.kicad_sym",+    "hcf4070ym013tr.kicad_mod",+    "hcf4070ym013tr.glb",+    "hcf4070ym013tr.step",+    "hcf4070ym013tr.lbr",+    "docs/hero.png",+    "docs/hcf4070ym013tr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "HCF4070YM013TR",+    "manufacturer": "STMicroelectronics",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.st.com/resource/en/datasheet/hcf4070ym013tr.pdf",+    "parts": {+      "symbol": "hcf4070ym013tr.kicad_sym",+      "footprint": "hcf4070ym013tr.kicad_mod",+      "model_3d": "hcf4070ym013tr-etched.glb",+      "model_3d_plain": "hcf4070ym013tr.glb",+      "model_3d_step": "hcf4070ym013tr-etched.step",+      "model_3d_step_plain": "hcf4070ym013tr.step",+      "lbr": "hcf4070ym013tr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2970521",+      "digikey": "497-14375-2-ND",+      "mouser": "511-HCF4070YM013TR"+    },+    "distributor_check": {+      "checked_at": "2026-10-01T06:42:54Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "497-14375-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "511-HCF4070YM013TR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Input A for XOR gate 1, accepts 0 to VDD V"+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Input B for XOR gate 1, accepts 0 to VDD V"+      },+      {+        "number": "3",+        "name": "J",+        "type": "output",+        "description": "Output from XOR gate 1, provides 0 to VDD V"+      },+      {+        "number": "4",+        "name": "K",+        "type": "output",+        "description": "Output from XOR gate 2, provides 0 to VDD V"+      },+      {+        "number": "5",+        "name": "C",+        "type": "input",+        "description": "Input C for XOR gate 2, accepts 0 to VDD V"+      },+      {+        "number": "6",+        "name": "D",+        "type": "input",+        "description": "Input D for XOR gate 2, accepts 0 to VDD V"+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground (negative supply voltage), 0 V reference"+      },+      {+        "number": "8",+        "name": "E",+        "type": "input",+        "description": "Input E for XOR gate 3, accepts 0 to VDD V"+      },+      {+        "number": "9",+        "name": "F",+        "type": "input",+        "description": "Input F for XOR gate 3, accepts 0 to VDD V"+      },+      {+        "number": "10",+        "name": "L",+        "type": "output",+        "description": "Output from XOR gate 3, provides 0 to VDD V"+      },+      {+        "number": "11",+        "name": "M",+        "type": "output",+        "description": "Output from XOR gate 4, provides 0 to VDD V"+      },+      {+        "number": "12",+        "name": "G",+        "type": "input",+        "description": "Input G for XOR gate 4, accepts 0 to VDD V"+      },+      {+        "number": "13",+        "name": "H",+        "type": "input",+        "description": "Input H for XOR gate 4, accepts 0 to VDD V"+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply voltage, 3 to 20 V nominal"+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 12,+        "cost_usd": 0.0911,+        "at": "2026-10-01T06:42:38"+      },+      "datasheet": {+        "url": "https://www.st.com/resource/en/datasheet/hcf4070ym013tr.pdf",+        "pages": 12,+        "sha256": "0a47eb12ec052f7d",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No 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