GN595D

@@ -0,0 +1,56 @@+# GN595D++**GN Semic** · Shifting Register · SOP-16++GN595D from GN Semic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q1 | tri_state | Parallel 3-state output bit 1 of the storage register. Drives up to +/-6 mA at Vcc=4.5 V. High-impedance when G is high. |+| 2 | Q2 | tri_state | Parallel 3-state output bit 2 of the storage register. Same drive characteristics as the other QN outputs; high-Z when G is high. |+| 3 | Q3 | tri_state | Parallel 3-state output bit 3 of the storage register. High-Z when G is high. |+| 4 | Q4 | tri_state | Parallel 3-state output bit 4 of the storage register. High-Z when G is high. |+| 5 | Q5 | tri_state | Parallel 3-state output bit 5 of the storage register. High-Z when G is high. |+| 6 | Q6 | tri_state | Parallel 3-state output bit 6 of the storage register. High-Z when G is high. |+| 7 | Q7 | tri_state | Parallel 3-state output bit 7 (MSB) of the storage register. High-Z when G is high. |+| 8 | GND | power_in | Ground reference (0 V) for the device. |+| 9 | Q7' | output | Serial data output from the last (8th) stage of the shift register. Used to cascade multiple GN595D devices to build longer shift chains; not affected by the output-enable G. |+| 10 | SCLR | input | Active-low shift-register clear. When held low, all shift-register bits are reset to 0 (Q7' = 0); does not affect the storage-register outputs. |+| 11 | SCK | input | Shift-register (data-input) clock. On a rising edge, SER is shifted into the shift register (QN = QN-1, Q0 = SER). Rated to typ. 91 MHz at Vcc=4.5 V, 108 MHz at Vcc=6 V. |+| 12 | RCK | input | Storage-register (output latch) clock. A rising edge latches the shift-register contents into the storage register, updating Q0-Q7. |+| 13 | G | input | Active-low output enable for the parallel outputs Q0-Q7. When high, Q0-Q7 are placed in the high-impedance state; when low, storage-register contents drive the outputs. |+| 14 | SER | input | Serial data input. Sampled on the rising edge of SCK and shifted into bit 0 of the shift register. |+| 15 | Q0 | tri_state | Parallel 3-state output bit 0 (LSB) of the storage register. High-Z when G is high. |+| 16 | Vcc | power_in | Positive supply, 2 V to 6 V (absolute max 7 V). Bypass locally with a ceramic capacitor (typ. 100 nF) to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GN Semic |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `GN595D`+- `GN595DGN595T`++## CAD (KiCad official)++- Symbol: `GN595D`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GN Semic datasheet](docs/gn595d-datasheet.pdf) (13 pp, sha256 `6570ea554171b0b3`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/gn595d-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "gn595d",+  "version": "0.1.0",+  "type": "component",+  "description": "GN Semic Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "gn595d"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "gn595d.kicad_sym",+    "gn595d.kicad_mod",+    "gn595d.glb",+    "gn595d.step",+    "gn595d.lbr",+    "docs/hero.png",+    "docs/gn595d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file