GN164D

@@ -42,6 +42,20 @@ GN164D from GN Semic, in a SOP-14. Pinout and pin descriptions extracted from th - Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm` - 3D model: SOP-14 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`gn164d.step`](gn164d.step) | 195 KB | You want the bare part, or you mark your own boards. |+| [`gn164d-etched.step`](gn164d-etched.step) | 1.6 MB | You want the part with `GN164D` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 422 faces against 237 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:

@@ -1,6 +1,6 @@ {   "slug": "gn164d",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "GN Semic Shifting Register, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [

@@ -4,7 +4,7 @@   "slug": "gn164d",   "title": "GN164D",   "brief": "GN Semic Shifting Register, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -34,7 +34,7 @@         "number": "1",         "name": "DSA",         "type": "input",-        "description": "Serial data input A. Internally ANDed with DSB to form the serial data bit clocked into the first stage of the shift register on the rising edge of CP. CMOS input levels; VIH \u2265 0.7\u00b7VCC, VIL \u2264 0.3\u00b7VCC (approximate over 2-6 V VCC)."+        "description": "Serial data input A. Internally ANDed with DSB to form the serial data bit clocked into the first stage of the shift register on the rising edge of CP. CMOS input levels; VIH ≥ 0.7·VCC, VIL ≤ 0.3·VCC (approximate over 2-6 V VCC)."       },       {         "number": "2",@@ -46,7 +46,7 @@         "number": "3",         "name": "Q0",         "type": "output",-        "description": "Parallel output bit 0 (first stage of the shift register). Push-pull CMOS output; drives up to 10 LSTTL loads. VOH \u2265 VCC\u22120.1 V at IO = \u221220 \u00b5A; VOL \u2264 0.1 V at IO = 20 \u00b5A."+        "description": "Parallel output bit 0 (first stage of the shift register). Push-pull CMOS output; drives up to 10 LSTTL loads. VOH ≥ VCC−0.1 V at IO = −20 µA; VOL ≤ 0.1 V at IO = 20 µA."       },       {         "number": "4",@@ -82,7 +82,7 @@         "number": "9",         "name": "MR",         "type": "input",-        "description": "Master reset, active-low (overbar). A low pulse asynchronously clears all eight output stages (Q0-Q7) to logic low, independent of CP. Minimum low pulse width tw \u2248 60 ns at VCC=2 V, 10 ns at VCC=6 V."+        "description": "Master reset, active-low (overbar). A low pulse asynchronously clears all eight output stages (Q0-Q7) to logic low, independent of CP. Minimum low pulse width tw ≈ 60 ns at VCC=2 V, 10 ns at VCC=6 V."       },       {         "number": "10",@@ -112,7 +112,7 @@         "number": "14",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage. Recommended operating range 2.0-6.0 V (typ 5.0 V); absolute maximum \u22120.5 to +7 V. Static supply current ICC \u2264 8 \u00b5A at VCC=6 V."+        "description": "Positive supply voltage. Recommended operating range 2.0-6.0 V (typ 5.0 V); absolute maximum −0.5 to +7 V. Static supply current ICC ≤ 8 µA at VCC=6 V."       }     ],     "provenance": {@@ -186,9 +186,9 @@     "docs/hero.png",     "docs/gn164d-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "GN Semic Shifting Register, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file