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orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C265482). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·e00d075ad4 · ·parent 8ede334
2 files changed +27−7
gn164d.lbr+20−2
@@ -68,6 +68,18 @@   <smd name="12" x="2.4750" y="1.2700" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="13" x="2.4750" y="2.5400" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="14" x="2.4750" y="3.8100" dx="1.9500" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="4.3700"/>+    <vertex x="-2.8400" y="4.7000"/>+    <vertex x="-2.3600" y="4.7000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="4.3250"/>+    <vertex x="1.9500" y="4.3250"/>+    <vertex x="1.9500" y="-4.3250"/>+    <vertex x="-1.9500" y="-4.3250"/>+    <vertex x="-1.9500" y="3.3500"/>+  </polygon>   <wire x1="-2.0600" y1="4.4350" x2="2.0600" y2="4.4350" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="4.3700" x2="-2.0600" y2="4.4350" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-4.4350" x2="-2.0600" y2="-4.3700" width="0.1200" layer="21"/>@@ -76,7 +88,7 @@   <wire x1="2.0600" y1="-4.4350" x2="-2.0600" y2="-4.4350" width="0.1200" layer="21"/>   <text x="0" y="5.385" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-5.385" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="4.3700"/><vertex x="-2.8400" y="4.7000"/><vertex x="-2.3600" y="4.7000"/></polygon></package>+</package> </packages> <symbols> <symbol name="GN164D">@@ -126,7 +138,13 @@         <connect gate="G$1" pin="MR" pad="9"/>         <connect gate="G$1" pin="CP" pad="8"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="GN164D" constant="no"/>+          <attribute name="MANUFACTURER" value="GN Semic" constant="no"/>+          <attribute name="LCSC_PN" value="C265482" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>
page.json+7−5
@@ -26,13 +26,15 @@       "model_3d_step": "gn164d.step",       "lbr": "gn164d.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C265482"+    },     "pins": [       {         "number": "1",         "name": "DSA",         "type": "input",-        "description": "Serial data input A. Internally ANDed with DSB to form the serial data bit clocked into the first stage of the shift register on the rising edge of CP. CMOS input levels; VIH ≥ 0.7·VCC, VIL ≤ 0.3·VCC (approximate over 2-6 V VCC)."+        "description": "Serial data input A. Internally ANDed with DSB to form the serial data bit clocked into the first stage of the shift register on the rising edge of CP. CMOS input levels; VIH \u2265 0.7\u00b7VCC, VIL \u2264 0.3\u00b7VCC (approximate over 2-6 V VCC)."       },       {         "number": "2",@@ -44,7 +46,7 @@         "number": "3",         "name": "Q0",         "type": "output",-        "description": "Parallel output bit 0 (first stage of the shift register). Push-pull CMOS output; drives up to 10 LSTTL loads. VOH ≥ VCC−0.1 V at IO = −20 µA; VOL ≤ 0.1 V at IO = 20 µA."+        "description": "Parallel output bit 0 (first stage of the shift register). Push-pull CMOS output; drives up to 10 LSTTL loads. VOH \u2265 VCC\u22120.1 V at IO = \u221220 \u00b5A; VOL \u2264 0.1 V at IO = 20 \u00b5A."       },       {         "number": "4",@@ -80,7 +82,7 @@         "number": "9",         "name": "MR",         "type": "input",-        "description": "Master reset, active-low (overbar). A low pulse asynchronously clears all eight output stages (Q0-Q7) to logic low, independent of CP. Minimum low pulse width tw ≈ 60 ns at VCC=2 V, 10 ns at VCC=6 V."+        "description": "Master reset, active-low (overbar). A low pulse asynchronously clears all eight output stages (Q0-Q7) to logic low, independent of CP. Minimum low pulse width tw \u2248 60 ns at VCC=2 V, 10 ns at VCC=6 V."       },       {         "number": "10",@@ -110,7 +112,7 @@         "number": "14",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage. Recommended operating range 2.0-6.0 V (typ 5.0 V); absolute maximum −0.5 to +7 V. Static supply current ICC ≤ 8 µA at VCC=6 V."+        "description": "Positive supply voltage. Recommended operating range 2.0-6.0 V (typ 5.0 V); absolute maximum \u22120.5 to +7 V. Static supply current ICC \u2264 8 \u00b5A at VCC=6 V."       }     ],     "provenance": {