GN164D

@@ -0,0 +1,53 @@+# GN164D++**GN Semic** · Shifting Register · SOP-14++GN164D from GN Semic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DSA | input | Serial data input A. Internally ANDed with DSB to form the serial data bit clocked into the first stage of the shift register on the rising edge of CP. CMOS input levels; VIH ≥ 0.7·VCC, VIL ≤ 0.3·VCC (approximate over 2-6 V VCC). |+| 2 | DSB | input | Serial data input B. Internally ANDed with DSA to form the serial data bit clocked into the shift register. Tie to VCC when unused so that DSA alone controls the serial stream. |+| 3 | Q0 | output | Parallel output bit 0 (first stage of the shift register). Push-pull CMOS output; drives up to 10 LSTTL loads. VOH ≥ VCC−0.1 V at IO = −20 µA; VOL ≤ 0.1 V at IO = 20 µA. |+| 4 | Q1 | output | Parallel output bit 1. Push-pull CMOS output, driven by the second flip-flop stage; asynchronously cleared low by MR. |+| 5 | Q2 | output | Parallel output bit 2. Push-pull CMOS output from the third flip-flop stage. |+| 6 | Q3 | output | Parallel output bit 3. Push-pull CMOS output from the fourth flip-flop stage. |+| 7 | GND | power_in | Ground reference, 0 V. Common return for supply and I/O. |+| 8 | CP | input | Clock input. Data on (DSA AND DSB) is shifted one position to the right on the low-to-high (rising) edge of CP. Max clock frequency 23 MHz typ at VCC=2 V, 71 MHz typ at 4.5 V, 85 MHz typ at 6 V. |+| 9 | MR | input | Master reset, active-low (overbar). A low pulse asynchronously clears all eight output stages (Q0-Q7) to logic low, independent of CP. Minimum low pulse width tw ≈ 60 ns at VCC=2 V, 10 ns at VCC=6 V. |+| 10 | Q4 | output | Parallel output bit 4. Push-pull CMOS output from the fifth flip-flop stage. |+| 11 | Q5 | output | Parallel output bit 5. Push-pull CMOS output from the sixth flip-flop stage. |+| 12 | Q6 | output | Parallel output bit 6. Push-pull CMOS output from the seventh flip-flop stage. |+| 13 | Q7 | output | Parallel output bit 7 (last stage of the shift register). Serves as the natural cascade output for chaining GN164D devices. |+| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 2.0-6.0 V (typ 5.0 V); absolute maximum −0.5 to +7 V. Static supply current ICC ≤ 8 µA at VCC=6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GN Semic |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `GN164DD`++## CAD (KiCad official)++- Symbol: `GN164D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GN Semic datasheet](docs/gn164d-datasheet.pdf) (9 pp, sha256 `d9a6400afbc41c6d`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/gn164d-datasheet.pdf)

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