component
GM1302
Public Made by Adomby adom
GATEMODE Real-time Clocks (RTC), SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C2845166). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+26−6
gm1302.lbr+20−2@@ -62,6 +62,18 @@ <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="2.4700"/>+ <vertex x="-2.8400" y="2.8000"/>+ <vertex x="-2.3600" y="2.8000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="2.4500"/>+ <vertex x="1.9500" y="2.4500"/>+ <vertex x="1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="1.4750"/>+ </polygon> <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -70,7 +82,7 @@ <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/> <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="GM1302">@@ -108,7 +120,13 @@ <connect gate="G$1" pin="I/O" pad="6"/> <connect gate="G$1" pin="RST" pad="5"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="GM1302" constant="no"/>+ <attribute name="MANUFACTURER" value="GATEMODE" constant="no"/>+ <attribute name="LCSC_PN" value="C2845166" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+6−4@@ -26,7 +26,9 @@ "model_3d_step": "gm1302.step", "lbr": "gm1302.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C2845166"+ }, "pins": [ { "number": "1",@@ -56,19 +58,19 @@ "number": "5", "name": "RST", "type": "input",- "description": "Reset / chip-enable input. Must be driven HIGH during any read/write to initiate a data transfer; driving it low terminates a transfer and places I/O in high-impedance. Contains an internal 40kΩ (typ) pull-down to ground. On power-up RST must be held logic 0 until Vcc ≥ 2.5V."+ "description": "Reset / chip-enable input. Must be driven HIGH during any read/write to initiate a data transfer; driving it low terminates a transfer and places I/O in high-impedance. Contains an internal 40k\u03a9 (typ) pull-down to ground. On power-up RST must be held logic 0 until Vcc \u2265 2.5V." }, { "number": "6", "name": "I/O", "type": "bidirectional",- "description": "Bidirectional serial data pin for the 3-wire interface (command/address in, data in/out). Contains an internal 40kΩ (typ) pull-down to ground. Goes high-impedance when RST is low or between output bits per SCLK rising edge. I/O capacitance C_I/O typ. 15 pF."+ "description": "Bidirectional serial data pin for the 3-wire interface (command/address in, data in/out). Contains an internal 40k\u03a9 (typ) pull-down to ground. Goes high-impedance when RST is low or between output bits per SCLK rising edge. I/O capacitance C_I/O typ. 15 pF." }, { "number": "7", "name": "SCLK", "type": "input",- "description": "Serial clock input for the 3-wire interface; synchronizes data transfers on the I/O pin. Data in is latched on the rising edge, data out is driven on the falling edge. Contains an internal 40kΩ (typ) pull-down. Max SCLK frequency 2 MHz at Vcc = 5V (0.5 MHz at Vcc = 2V)."+ "description": "Serial clock input for the 3-wire interface; synchronizes data transfers on the I/O pin. Data in is latched on the rising edge, data out is driven on the falling edge. Contains an internal 40k\u03a9 (typ) pull-down. Max SCLK frequency 2 MHz at Vcc = 5V (0.5 MHz at Vcc = 2V)." }, { "number": "8",