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Set visibility: public

Ray ·ab9a639325 · ·parent ad0fde5
1 file changed +7−4
page.json+7−4
@@ -56,19 +56,19 @@         "number": "5",         "name": "RST",         "type": "input",-        "description": "Reset / chip-enable input. Must be driven HIGH during any read/write to initiate a data transfer; driving it low terminates a transfer and places I/O in high-impedance. Contains an internal 40k\u03a9 (typ) pull-down to ground. On power-up RST must be held logic 0 until Vcc \u2265 2.5V."+        "description": "Reset / chip-enable input. Must be driven HIGH during any read/write to initiate a data transfer; driving it low terminates a transfer and places I/O in high-impedance. Contains an internal 40kΩ (typ) pull-down to ground. On power-up RST must be held logic 0 until Vcc ≥ 2.5V."       },       {         "number": "6",         "name": "I/O",         "type": "bidirectional",-        "description": "Bidirectional serial data pin for the 3-wire interface (command/address in, data in/out). Contains an internal 40k\u03a9 (typ) pull-down to ground. Goes high-impedance when RST is low or between output bits per SCLK rising edge. I/O capacitance C_I/O typ. 15 pF."+        "description": "Bidirectional serial data pin for the 3-wire interface (command/address in, data in/out). Contains an internal 40kΩ (typ) pull-down to ground. Goes high-impedance when RST is low or between output bits per SCLK rising edge. I/O capacitance C_I/O typ. 15 pF."       },       {         "number": "7",         "name": "SCLK",         "type": "input",-        "description": "Serial clock input for the 3-wire interface; synchronizes data transfers on the I/O pin. Data in is latched on the rising edge, data out is driven on the falling edge. Contains an internal 40k\u03a9 (typ) pull-down. Max SCLK frequency 2 MHz at Vcc = 5V (0.5 MHz at Vcc = 2V)."+        "description": "Serial clock input for the 3-wire interface; synchronizes data transfers on the I/O pin. Data in is latched on the rising edge, data out is driven on the falling edge. Contains an internal 40kΩ (typ) pull-down. Max SCLK frequency 2 MHz at Vcc = 5V (0.5 MHz at Vcc = 2V)."       },       {         "number": "8",@@ -138,5 +138,8 @@     "docs/gm1302-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file