component
GL850G-HHY22
Public Made by Adomby adom
Genesys Logic USB Converters, SSOP-28-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C136617). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+27−7
gl850g-hhy22.lbr+20−2@@ -82,6 +82,18 @@ <smd name="26" x="3.5000" y="2.9250" dx="1.9000" dy="0.4000" layer="1"/> <smd name="27" x="3.5000" y="3.5750" dx="1.9000" dy="0.4000" layer="1"/> <smd name="28" x="3.5000" y="4.2250" dx="1.9000" dy="0.4000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-3.5000" y="4.6900"/>+ <vertex x="-3.8400" y="5.1600"/>+ <vertex x="-3.1600" y="5.1600"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-1.6500" y="5.1000"/>+ <vertex x="2.6500" y="5.1000"/>+ <vertex x="2.6500" y="-5.1000"/>+ <vertex x="-2.6500" y="-5.1000"/>+ <vertex x="-2.6500" y="4.1000"/>+ </polygon> <wire x1="-2.7600" y1="5.2100" x2="2.7600" y2="5.2100" width="0.1200" layer="21"/> <wire x1="-2.7600" y1="4.6850" x2="-2.7600" y2="5.2100" width="0.1200" layer="21"/> <wire x1="-2.7600" y1="-5.2100" x2="-2.7600" y2="-4.6850" width="0.1200" layer="21"/>@@ -90,7 +102,7 @@ <wire x1="2.7600" y1="-5.2100" x2="-2.7600" y2="-5.2100" width="0.1200" layer="21"/> <text x="0" y="5.810" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-5.810" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-3.5000" y="4.6900"/><vertex x="-3.8400" y="5.1600"/><vertex x="-3.1600" y="5.1600"/></polygon></package>+</package> </packages> <symbols> <symbol name="GL850G-HHY22">@@ -168,7 +180,13 @@ <connect gate="G$1" pin="DVDD" pad="16"/> <connect gate="G$1" pin="GND" pad="15"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="GL850G-HHY22" constant="no"/>+ <attribute name="MANUFACTURER" value="Genesys Logic" constant="no"/>+ <attribute name="LCSC_PN" value="C136617" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+7−5@@ -26,7 +26,9 @@ "model_3d_step": "gl850g-hhy22.step", "lbr": "gl850g-hhy22.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C136617"+ }, "pins": [ { "number": "1",@@ -50,7 +52,7 @@ "number": "4", "name": "RREF", "type": "passive",- "description": "USB PHY bias reference. Connect a 680 Ω resistor from RREF to AGND to set the USB transmitter bias current."+ "description": "USB PHY bias reference. Connect a 680 \u03a9 resistor from RREF to AGND to set the USB transmitter bias current." }, { "number": "5",@@ -104,7 +106,7 @@ "number": "13", "name": "RESET#", "type": "input",- "description": "Active-low external reset input, 5 V tolerant. Internally pulled high through ~10 kΩ. Drive low to reset the whole chip."+ "description": "Active-low external reset input, 5 V tolerant. Internally pulled high through ~10 k\u03a9. Drive low to reset the whole chip." }, { "number": "14",@@ -164,13 +166,13 @@ "number": "23", "name": "V5", "type": "power_in",- "description": "5 V power input to the on-chip 5 V→3.3 V regulator. Leave NC when using an external 3.3 V regulator."+ "description": "5 V power input to the on-chip 5 V\u21923.3 V regulator. Leave NC when using an external 3.3 V regulator." }, { "number": "24", "name": "V33", "type": "power_out",- "description": "5 V→3.3 V regulator output AND 3.3 V supply pin (SSOP-28/QFN-28). Bypass to ground; also drives AVDD/DVDD externally."+ "description": "5 V\u21923.3 V regulator output AND 3.3 V supply pin (SSOP-28/QFN-28). Bypass to ground; also drives AVDD/DVDD externally." }, { "number": "25",