GD32F405RGT6

@@ -0,0 +1,111 @@+# GD32F405RGT6++**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++GD32F405RGT6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup domain power supply. Powers the RTC, LXTAL oscillator, and backup registers when VDD is absent (typ 1.8 V to 3.6 V). |+| 2 | PC13/TAMPER-RTC | bidirectional | General-purpose I/O PC13, 5 V tolerant. Alternate: EVENTOUT. Additional: RTC_TAMP0, RTC_OUT, RTC_TS. Powered from VBAT domain; limited drive strength. |+| 3 | PC14/OSC32_IN | bidirectional | General-purpose I/O PC14, 5 V tolerant. Additional function: OSC32IN input for the 32.768 kHz LXTAL crystal oscillator. |+| 4 | PC15/OSC32_OUT | bidirectional | General-purpose I/O PC15, 5 V tolerant. Additional function: OSC32OUT output for the 32.768 kHz LXTAL crystal oscillator. |+| 5 | PH0/OSC_IN | bidirectional | General-purpose I/O PH0, 5 V tolerant. Additional function: OSCIN input for the HXTAL (main) crystal oscillator, 4-26 MHz. |+| 6 | PH1/OSC_OUT | bidirectional | General-purpose I/O PH1, 5 V tolerant. Additional function: OSCOUT return of the HXTAL crystal oscillator. |+| 7 | NRST | input | Active-low bidirectional reset input with internal pull-up. Drive low to reset the MCU; internally driven low when the on-chip POR/PDR asserts. |+| 8 | PC0 | bidirectional | GPIO PC0, 5 V tolerant. Alternate: USBHS_ULPI_STP, EVENTOUT. Additional: ADC012_IN10 analog input. |+| 9 | PC1 | bidirectional | GPIO PC1, 5 V tolerant. Alternate: SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT. Additional: ADC012_IN11. |+| 10 | PC2 | bidirectional | GPIO PC2, 5 V tolerant. Alternate: SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, EVENTOUT. Additional: ADC012_IN12. |+| 11 | PC3 | bidirectional | GPIO PC3, 5 V tolerant. Alternate: SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, EVENTOUT. Additional: ADC012_IN13. |+| 12 | VSSA | power_in | Analog ground reference for the ADC/DAC and VREF+ path. Tie to the board ground plane, ideally at a single star point with VSS. |+| 13 | VDDA | power_in | Analog supply for the ADC/DAC/reset/PLL blocks, 2.6-3.6 V. Decouple with 100 nF + 1 µF close to the pin; also serves as internal VREF+ when VREF+ is absent. |+| 14 | PA0-WKUP | bidirectional | GPIO PA0, 5 V tolerant. Alternate: TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, EVENTOUT. Additional: ADC012_IN0, WKUP (Standby wake-up). |+| 15 | PA1 | bidirectional | GPIO PA1, 5 V tolerant. Alternate: TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT. Additional: ADC012_IN1. |+| 16 | PA2 | bidirectional | GPIO PA2, 5 V tolerant. Alternate: TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT. Additional: ADC012_IN2. |+| 17 | PA3 | bidirectional | GPIO PA3, 5 V tolerant. Alternate: TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, EVENTOUT. Additional: ADC012_IN3. |+| 18 | VSS | power_in | Digital ground return. Multiple VSS pins must all connect to the board ground plane. |+| 19 | VDD | power_in | Digital I/O and core LDO supply, 2.6-3.6 V. Decouple each VDD pin with a 100 nF ceramic capacitor close to the pin plus a bulk 4.7 µF. |+| 20 | PA4 | bidirectional | GPIO PA4, TTa (analog) 3.3 V level. Alternate: SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, EVENTOUT. Additional: ADC01_IN4, DAC_OUT0. |+| 21 | PA5 | bidirectional | GPIO PA5, TTa (analog) 3.3 V level. Alternate: TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT. Additional: ADC01_IN5, DAC_OUT1. |+| 22 | PA6 | bidirectional | GPIO PA6, 5 V tolerant. Alternate: TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT. Additional: ADC01_IN6. |+| 23 | PA7 | bidirectional | GPIO PA7, 5 V tolerant. Alternate: TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, EVENTOUT. Additional: ADC01_IN7. |+| 24 | PC4 | bidirectional | GPIO PC4, 5 V tolerant. Alternate: EVENTOUT. Additional: ADC01_IN14. |+| 25 | PC5 | bidirectional | GPIO PC5, 5 V tolerant. Alternate: USART2_RX, EVENTOUT. Additional: ADC01_IN15. |+| 26 | PB0 | bidirectional | GPIO PB0, 5 V tolerant. Alternate: TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, SDIO_D1, EVENTOUT. Additional: ADC01_IN8, IREF. |+| 27 | PB1 | bidirectional | GPIO PB1, 5 V tolerant. Alternate: TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, SDIO_D2, EVENTOUT. Additional: ADC01_IN9. |+| 28 | PB2/BOOT1 | bidirectional | GPIO PB2, 5 V tolerant. Alternate: TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT. Sampled at reset as BOOT1 to select the boot mode together with BOOT0. |+| 29 | PB10 | bidirectional | GPIO PB10, 5 V tolerant. Alternate: TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, SDIO_D7, EVENTOUT. |+| 30 | PB11 | bidirectional | GPIO PB11, 5 V tolerant. Alternate: TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, EVENTOUT. |+| 31 | VCAP1 | power_out | Internal 1.2 V core LDO output (labelled NC / VCORE in the LQFP64 pinout). Must be connected to a 2.2 µF ceramic decoupling capacitor to VSS; do not connect to any external supply. |+| 32 | VDD | power_in | Digital I/O and core LDO supply, 2.6-3.6 V. Decouple with 100 nF close to the pin. |+| 33 | PB12 | bidirectional | GPIO PB12, 5 V tolerant. Alternate: TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT. |+| 34 | PB13 | bidirectional | GPIO PB13, 5 V tolerant. Alternate: TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME. Additional: USBHS_VBUS. |+| 35 | PB14 | bidirectional | GPIO PB14, 5 V tolerant. Alternate: TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT. |+| 36 | PB15 | bidirectional | GPIO PB15, 5 V tolerant. Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT. |+| 37 | PC6 | bidirectional | GPIO PC6, 5 V tolerant. Alternate: TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT. |+| 38 | PC7 | bidirectional | GPIO PC7, 5 V tolerant. Alternate: TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT. |+| 39 | PC8 | bidirectional | GPIO PC8, 5 V tolerant. Alternate: TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT. |+| 40 | PC9 | bidirectional | GPIO PC9, 5 V tolerant. Alternate: CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT. |+| 41 | PA8 | bidirectional | GPIO PA8, 5 V tolerant. Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC. |+| 42 | PA9 | bidirectional | GPIO PA9, 5 V tolerant. Alternate: TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT. Additional: USBFS_VBUS. |+| 43 | PA10 | bidirectional | GPIO PA10, 5 V tolerant. Alternate: TIMER0_CH2, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME. |+| 44 | PA11 | bidirectional | GPIO PA11, 5 V tolerant. Alternate: TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT. |+| 45 | PA12 | bidirectional | GPIO PA12, 5 V tolerant. Alternate: TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT. |+| 46 | PA13/JTMS/SWDIO | bidirectional | SW/JTAG data I/O and GPIO PA13, 5 V tolerant. Default function after reset is JTMS/SWDIO for debug; re-mappable to GPIO PA13 or EVENTOUT. |+| 47 | NC | unconnected | No connect. Leave floating; do not connect to VDD, VSS, or any other net. |+| 48 | VDD | power_in | Digital supply, 2.6-3.6 V. Decouple with 100 nF close to the pin. (Labelled VDD_2 in the pinout diagram.) |+| 49 | PA14/JTCK/SWCLK | bidirectional | SW/JTAG clock and GPIO PA14, 5 V tolerant. Default function after reset is JTCK/SWCLK for debug; re-mappable to GPIO PA14 or EVENTOUT. |+| 50 | PA15/JTDI | bidirectional | JTAG data in and GPIO PA15, 5 V tolerant. Default at reset is JTDI. Alternate: TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT. |+| 51 | PC10 | bidirectional | GPIO PC10, 5 V tolerant. Alternate: SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT. |+| 52 | PC11 | bidirectional | GPIO PC11, 5 V tolerant. Alternate: I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT. |+| 53 | PC12 | bidirectional | GPIO PC12, 5 V tolerant. Alternate: I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT. |+| 54 | PD2 | bidirectional | GPIO PD2, 5 V tolerant. Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT. |+| 55 | PB3/JTDO | bidirectional | JTDO/SWO trace and GPIO PB3, 5 V tolerant. Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT. |+| 56 | PB4/NJTRST | bidirectional | JTAG reset (NJTRST) and GPIO PB4, 5 V tolerant. Alternate: TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME. |+| 57 | PB5 | bidirectional | GPIO PB5, 5 V tolerant. Alternate: TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT, DCI_D10, EVENTOUT. |+| 58 | PB6 | bidirectional | GPIO PB6, 5 V tolerant. Alternate: TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT. |+| 59 | PB7 | bidirectional | GPIO PB7, 5 V tolerant. Alternate: TIMER3_CH1, I2C0_SDA, USART0_RX, DCI_VSYNC, EVENTOUT. |+| 60 | BOOT0 | input | Boot-mode select input latched at reset. Together with PB2/BOOT1 it selects boot from main Flash, system memory (bootloader), or embedded SRAM. |+| 61 | PB8 | bidirectional | GPIO PB8, 5 V tolerant. Alternate: TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT. |+| 62 | PB9 | bidirectional | GPIO PB9, 5 V tolerant. Alternate: TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT. |+| 63 | VSS | power_in | Digital ground return. |+| 64 | VDD | power_in | Digital supply, 2.6-3.6 V. Decouple with 100 nF close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GigaDevice Semicon Beijing |+| Package | LQFP-64(10x10) |+| Category | MCU |+| Pins | 64 |++## Ordering variants++- `GD32F405RGT6RET6`+- `GD32F405RGT6RGT6`+- `GD32F405RGT6RKT6`+- `GD32F405RGT6VGT6`+- `GD32F405RGT6VKT6`+- `GD32F405RGT6VGH6`+- `GD32F405RGT6VKH6`+- `GD32F405RGT6ZGT6`+- `GD32F405RGT6ZKT6`++## CAD (KiCad official)++- Symbol: `GD32F405RGT6`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GigaDevice Semicon Beijing datasheet](docs/gd32f405rgt6-datasheet.pdf) (60 pp, sha256 `824ce8ab21b66f5d`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/gd32f405rgt6-datasheet.pdf)