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gd25q80esigr: factory component page (tier=lcsc)

Ray ·c960642af6 · ·parent 326ad77
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "gd25q80esigr",+  "title": "GD25Q80ESIGR",+  "brief": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "gd25q80esigr"   ],+  "component": {+    "mpn": "GD25Q80ESIGR",+    "manufacturer": "GigaDevice Semicon Beijing",+    "package": "SOP-8-208mil",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "NOR FLASH",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2111191730_GigaDevice-Semicon-Beijing-GD25Q80ESIGR_C2922791.pdf",+    "parts": {+      "symbol": "gd25q80esigr.kicad_sym",+      "footprint": "gd25q80esigr.kicad_mod",+      "model_3d": "gd25q80esigr.glb",+      "model_3d_step": "gd25q80esigr.step",+      "lbr": "gd25q80esigr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "CS#",+        "type": "input",+        "description": "Chip Select input, active low. Drive high to deselect the device (must not float once power is applied). A high-to-low transition enables a command; a low-to-high transition ends the current operation."+      },+      {+        "number": "2",+        "name": "SO/IO1",+        "type": "bidirectional",+        "description": "Serial data output in Standard SPI mode; becomes bidirectional data I/O bit 1 in Dual/Quad SPI modes. Data shifts out on the falling edge of SCLK."+      },+      {+        "number": "3",+        "name": "WP#/IO2",+        "type": "bidirectional",+        "description": "Write Protect input (active low) in Standard/Dual SPI modes, used with Status Register BP/SRP bits to hardware-protect the device. Becomes bidirectional data I/O bit 2 when Quad SPI is enabled (QE=1)."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Device ground reference (0 V)."+      },+      {+        "number": "5",+        "name": "SI/IO0",+        "type": "bidirectional",+        "description": "Serial data input in Standard SPI mode (command, address and data are latched on the rising edge of SCLK). Becomes bidirectional data I/O bit 0 in Dual/Quad SPI modes."+      },+      {+        "number": "6",+        "name": "SCLK",+        "type": "input",+        "description": "Serial Clock input. Provides the timing reference for all serial input/output; up to 133 MHz for fast read with 30 pF load. Supports SPI modes 0 and 3."+      },+      {+        "number": "7",+        "name": "HOLD#/IO3",+        "type": "bidirectional",+        "description": "Hold input (active low), pauses serial communication without deselecting the device when Quad mode is disabled (QE=0). Becomes bidirectional data I/O bit 3 when Quad SPI is enabled (QE=1); the HOLD function is then disabled."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Core and I/O power supply. Full operating voltage range 2.7-3.6 V (single supply)."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2111191730_GigaDevice-Semicon-Beijing-GD25Q80ESIGR_C2922791.pdf",+        "pages": 56,+        "sha256": "d73ddac270234097",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GigaDevice Semicon Beijing",+      "Package": "SOP-8-208mil",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "gd25q80esigr"+  ],+  "discovery_pitch": "GD25Q80ESIGR (GigaDevice Semicon Beijing) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/gd25q80esigr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file