GD25Q80ESIGR

@@ -0,0 +1,69 @@+# GD25Q80ESIGR++**GigaDevice Semicon Beijing** · NOR FLASH · SOP-8-208mil++GD25Q80ESIGR from GigaDevice Semicon Beijing, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS# | input | Chip Select input, active low. Drive high to deselect the device (must not float once power is applied). A high-to-low transition enables a command; a low-to-high transition ends the current operation. |+| 2 | SO/IO1 | bidirectional | Serial data output in Standard SPI mode; becomes bidirectional data I/O bit 1 in Dual/Quad SPI modes. Data shifts out on the falling edge of SCLK. |+| 3 | WP#/IO2 | bidirectional | Write Protect input (active low) in Standard/Dual SPI modes, used with Status Register BP/SRP bits to hardware-protect the device. Becomes bidirectional data I/O bit 2 when Quad SPI is enabled (QE=1). |+| 4 | VSS | power_in | Device ground reference (0 V). |+| 5 | SI/IO0 | bidirectional | Serial data input in Standard SPI mode (command, address and data are latched on the rising edge of SCLK). Becomes bidirectional data I/O bit 0 in Dual/Quad SPI modes. |+| 6 | SCLK | input | Serial Clock input. Provides the timing reference for all serial input/output; up to 133 MHz for fast read with 30 pF load. Supports SPI modes 0 and 3. |+| 7 | HOLD#/IO3 | bidirectional | Hold input (active low), pauses serial communication without deselecting the device when Quad mode is disabled (QE=0). Becomes bidirectional data I/O bit 3 when Quad SPI is enabled (QE=1); the HOLD function is then disabled. |+| 8 | VCC | power_in | Core and I/O power supply. Full operating voltage range 2.7-3.6 V (single supply). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GigaDevice Semicon Beijing |+| Package | SOP-8-208mil |+| Category | Memory |+| Pins | 8 |++## Ordering variants++- `GD25Q80ESIGRSIG`+- `GD25Q80ESIGRSIGR`+- `GD25Q80ESIGRSIGT`+- `GD25Q80ESIGRSIGY`+- `GD25Q80ESIGRSJG`+- `GD25Q80ESIGRSEG`+- `GD25Q80ESIGRSFG`+- `GD25Q80ESIGRTIG`+- `GD25Q80ESIGRTJG`+- `GD25Q80ESIGRTEG`+- `GD25Q80ESIGRTFG`+- `GD25Q80ESIGREIG`+- `GD25Q80ESIGREJG`+- `GD25Q80ESIGREEG`+- `GD25Q80ESIGREFG`+- `GD25Q80ESIGRNIG`+- `GD25Q80ESIGRNJG`+- `GD25Q80ESIGRNEG`+- `GD25Q80ESIGRNFG`+- `GD25Q80ESIGRWIG`+- `GD25Q80ESIGRWJG`+- `GD25Q80ESIGRWEG`+- `GD25Q80ESIGRWFG`++## CAD (KiCad official)++- Symbol: `GD25Q80ESIGR`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8-208mil (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GigaDevice Semicon Beijing datasheet](docs/gd25q80esigr-datasheet.pdf) (56 pp, sha256 `d73ddac270234097`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/gd25q80esigr-datasheet.pdf)

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