← Commit history

gd25q16esigr: factory component page (tier=lcsc)

Ray ·90e8238106 · ·parent 20c6033
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "gd25q16esigr",+  "title": "GD25Q16ESIGR",+  "brief": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "gd25q16esigr"   ],+  "component": {+    "mpn": "GD25Q16ESIGR",+    "manufacturer": "GigaDevice Semicon Beijing",+    "package": "SOP-8-208mil",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "NOR FLASH",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2111191730_GigaDevice-Semicon-Beijing-GD25Q16ESIGR_C2922792.pdf",+    "parts": {+      "symbol": "gd25q16esigr.kicad_sym",+      "footprint": "gd25q16esigr.kicad_mod",+      "model_3d": "gd25q16esigr.glb",+      "model_3d_step": "gd25q16esigr.step",+      "lbr": "gd25q16esigr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "CS#",+        "type": "input",+        "description": "Chip Select input, active low. Must be driven high when the device is not selected; do not leave floating after power-on. Selects the flash for all SPI/Dual/Quad transactions."+      },+      {+        "number": "2",+        "name": "SO/IO1",+        "type": "bidirectional",+        "description": "Standard SPI serial data output (SO). In Dual/Quad SPI modes this pin becomes bidirectional data line IO1. Data is shifted out on the falling edge of SCLK."+      },+      {+        "number": "3",+        "name": "WP#/IO2",+        "type": "bidirectional",+        "description": "Write Protect input (active low) that hardware-locks the status register when QE=0. When the non-volatile Quad Enable (QE) bit in the Status Register is set to 1, this pin becomes bidirectional Quad SPI data line IO2."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Ground reference for the device. Connect directly to system ground."+      },+      {+        "number": "5",+        "name": "SI/IO0",+        "type": "bidirectional",+        "description": "Standard SPI serial data input (SI); latched on the rising edge of SCLK. In Dual/Quad SPI modes this pin becomes bidirectional data line IO0."+      },+      {+        "number": "6",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input; supports SPI modes 0 and 3, up to 133 MHz (with 30 pF load, VCC 3.0-3.6 V). Input data is latched on the rising edge and output data shifts on the falling edge."+      },+      {+        "number": "7",+        "name": "HOLD#/IO3",+        "type": "bidirectional",+        "description": "Hold input (active low) that pauses serial communication without deselecting the device when QE=0. When QE=1, this pin becomes bidirectional Quad SPI data line IO3."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Single power supply, 2.7 V to 3.6 V (full voltage range). Requires local decoupling; device auto-resets below the write-inhibit threshold VWI."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2111191730_GigaDevice-Semicon-Beijing-GD25Q16ESIGR_C2922792.pdf",+        "pages": 58,+        "sha256": "e664882f90d940a2",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GigaDevice Semicon Beijing",+      "Package": "SOP-8-208mil",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "gd25q16esigr"+  ],+  "discovery_pitch": "GD25Q16ESIGR (GigaDevice Semicon Beijing) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/gd25q16esigr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file