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gd25q128esig: factory component page (tier=lcsc)

Ray ·f4954bf2fa · ·parent 2132e0d
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "gd25q128esig",+  "title": "GD25Q128ESIG",+  "brief": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "memory",     "gd25q128esig"   ],+  "component": {+    "mpn": "GD25Q128ESIG",+    "manufacturer": "GigaDevice Semicon Beijing",+    "package": "SOP-8-208mil",+    "pin_count": 8,+    "category": "Memory",+    "subcategory": "NOR FLASH",+    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2106062244_GigaDevice-Semicon-Beijing-GD25Q128ESIG_C2758105.pdf",+    "parts": {+      "symbol": "gd25q128esig.kicad_sym",+      "footprint": "gd25q128esig.kicad_mod",+      "model_3d": "gd25q128esig.glb",+      "model_3d_step": "gd25q128esig.step",+      "lbr": "gd25q128esig.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "CS#",+        "type": "input",+        "description": "Chip Select input (active low). Must be driven high when the chip is not selected; do not leave floating after power-on. Enables the SPI interface and command decoding when asserted low."+      },+      {+        "number": "2",+        "name": "SO/IO1",+        "type": "bidirectional",+        "description": "Serial Data Output in Standard SPI mode; becomes bidirectional data line IO1 in Dual and Quad SPI modes. Shifts out on falling edge of SCLK in standard mode."+      },+      {+        "number": "3",+        "name": "WP#/IO2",+        "type": "bidirectional",+        "description": "Write Protect input (active low) in Standard/Dual SPI modes, protecting the Status Register BP/SRP bits when SRP=1. Becomes bidirectional data line IO2 in Quad SPI mode when the QE bit in Status Register is set to 1."+      },+      {+        "number": "4",+        "name": "VSS",+        "type": "power_in",+        "description": "Device ground reference (0V)."+      },+      {+        "number": "5",+        "name": "SI/IO0",+        "type": "bidirectional",+        "description": "Serial Data Input in Standard SPI mode; becomes bidirectional data line IO0 in Dual and Quad SPI modes. Data is latched on the rising edge of SCLK in standard mode."+      },+      {+        "number": "6",+        "name": "SCLK",+        "type": "input",+        "description": "Serial Clock input. Supports SPI modes 0 and 3, up to 133MHz for fast reads with 30pF load. Provides timing reference for all serial input/output."+      },+      {+        "number": "7",+        "name": "HOLD#/RESET#/IO3",+        "type": "bidirectional",+        "description": "Multi-function pin: acts as HOLD# input when HOLD/RST bit=0 (pauses serial communication when driven low), as RESET# input when HOLD/RST bit=1 (dedicated hardware reset with tRLRH \u2265 1\u00b5s), or as bidirectional data line IO3 in Quad SPI mode when QE=1."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Single power supply input, full voltage range 2.7V to 3.6V. Should be decoupled to VSS with a local bypass capacitor."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2106062244_GigaDevice-Semicon-Beijing-GD25Q128ESIG_C2758105.pdf",+        "pages": 63,+        "sha256": "54cb85133a09da0c",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "GigaDevice Semicon Beijing",+      "Package": "SOP-8-208mil",+      "Category": "Memory",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "gd25q128esig"+  ],+  "discovery_pitch": "GD25Q128ESIG (GigaDevice Semicon Beijing) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/gd25q128esig-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file