Fusion - the Fusion 360 Bridge

@@ -144,7 +144,7 @@ Canonical: https://wiki.adom.inc/adom/fusion-bridge · GitHub backup: `adom-inc/   the picture to a container caller automatically. Old keys stay. - `fusion_set_design_rules` takes `druText` or `druBase64`: a rules file that exists only on the caller's side is   staged on the box and loaded. That replaces ab's removed CLI helper `fusion_load_design_rules`; its other removed-  helper, `fusion_apply_instapcb_rules`, is `fusion_set_design_rules` with no fab (page issue #96).+  helper, the one that applied the bundled fab rules, is `fusion_set_design_rules` with no fab (page issue #96).  ## 1.10.36 (2026-09-22) @@ -518,7 +518,7 @@ Answers to the 1.10.2 acceptance on AdomLapper (page issues #81 and #82): - `fusion_routing_drc` reports `layer`, `x`, `y` (mm) per error, a `summary` by description,   and a note when Overlap warnings are same-signal joints. - `fusion_set_design_rules` scans the downloaded profile and returns `ruleWarnings` for a-  same-signal Copper Clearance over an all/all or trace scope. The InstaPCB 2L profile (and+  same-signal Copper Clearance over an all/all or trace scope. The 3rd party fab 2L profile (and   every other generated profile on adom/pcb-design-rules) carries "Same-net track spacing"   (0.25 mm, all/all, samesignal=yes); on the six-net fixture native DRC reports it as 31   Overlap warnings at the 13 pad entries and 18 trace/via joints. With that one rule disabled

@@ -343,7 +343,7 @@ Older history for the Adom Bridge Fusion 360 bridge. Recent versions are in the - **Bridge-SDK re-audit against the updated SDK.** (1) `bridge.json` `verbs[]` re-synced to the   authoritative `fusion_describe` catalog (was stale: 40 → 53 verbs; added the library/3D + board +   app-state verbs; `statusVerb` `fusion_get_app_state` is now listed; dropped the dead-  `fusion_apply_instapcb_rules`). (2) The USER skill's cold-start section now encodes all **8** SDK+  bundled-fab-rules verb). (2) The USER skill's cold-start section now encodes all **8** SDK   conventions (was 5), led by an `errorCode` response→meaning→action table (incl. the new   `addin_stale` row) and the reuse-don't-relaunch + surface-`_hint`-verbatim conventions. 

@@ -352,7 +352,7 @@ promptly with `statusVerb: fusion_get_app_state` - the AI polls instead of block fab checks. The rule packs live on the wiki page [adom/pcb-design-rules](https://wiki.adom.inc/adom/pcb-design-rules) (JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB and-Adom InstaPCB), one `.edru` per vendor, process and layer count.+the 3rd party fab), one `.edru` per vendor, process and layer count.  ```bash adom-bridge fusion_set_design_rules '{"action":"list"}'                 # every fab, process, layers row (no Fusion needed)@@ -360,7 +360,7 @@ adom-bridge fusion_set_design_rules '{"fab":"jlcpcb","layers":"2"}'     # fetch, adom-bridge fusion_set_design_rules '{"druPath":"C:/tmp/house.edru"}'   # a local rule file as-is ``` -With no `fab` the bundled Adom InstaPCB rules load, and `layers` auto-detects from the open board.+With no `fab` the bundled 3rd party fab rules load, and `layers` auto-detects from the open board. The reply carries `ruleWarnings` when the profile has a same-signal Copper Clearance rule over an all/all or trace scope, which native DRC reports as Overlap warnings at every pad entry and trace joint. Confirm the load with `fusion_alerts`: a refused file is an in-canvas toast, never a dialog.

@@ -5,7 +5,7 @@ Electronics workspace and write industry-standard output files:   - Gerbers (RS-274X) + Excellon drill files via EAGLE CAM processor   - BOM (Bill of Materials) CSV for component purchasing   - CPL (Component Placement List) CSV for pick-and-place assembly-  - Design rules (DRU) injection for Adom's InstapcbPCB manufacturing capabilities+  - Design rules (DRU) injection for the 3rd party fab's manufacturing capabilities  All three export commands require a .brd board to be open in PCB Editor. @@ -769,11 +769,11 @@ def _parse_edru_description(edru_path: str) -> str:   def handle_set_design_rules(app: adsk.core.Application, args: dict) -> dict:-    """Set PCB design rules in the open board to match Adom's manufacturing capabilities.+    """Set PCB design rules in the open board to match the 3rd party fab's manufacturing capabilities.      Loads a bundled .edru design rules file via EAGLE's `drc load` command.-    The .edru files are industry-tested rules from JLCPCB, adapted for Adom's-    InstapcbPCB manufacturing process.+    The .edru files are industry-tested rules from JLCPCB, adapted for the 3rd party+    fab's manufacturing process.      Auto-detects 2-layer vs 4-layer boards and loads the appropriate rule set. @@ -796,7 +796,7 @@ def handle_set_design_rules(app: adsk.core.Application, args: dict) -> dict:          return {             "success": True,-            "output": "Adom InstaPCB design rules (from bundled .edru files)",+            "output": "3rd party fab design rules (from bundled .edru files)",             "data": {                 "2layer_rules": desc_2 or "2-layer .edru file not found",                 "4layer_rules": desc_4 or "4-layer .edru file not found",@@ -850,7 +850,7 @@ def handle_set_design_rules(app: adsk.core.Application, args: dict) -> dict:         detection_method = detection["method"]      # Resolve the .edru file: a fab pack the bridge staged (druPath, fetched from the wiki page-    # adom/pcb-design-rules), else the bundled Adom InstaPCB rules for this layer count.+    # adom/pcb-design-rules), else the bundled 3rd party fab rules for this layer count.     dru_path_arg = (args.get("druPath") or "").replace("\\", "/")     if dru_path_arg:         edru_path = dru_path_arg@@ -893,7 +893,7 @@ def handle_set_design_rules(app: adsk.core.Application, args: dict) -> dict:         "message": (             (f"Design rules from {edru_filename} are now active. Rule violations will now show as "              f"DRC markers in the board editor.") if dru_path_arg else-            (f"Adom InstaPCB {layer_count}-Layer design rules are now active. "+            (f"3rd party fab {layer_count}-Layer design rules are now active. "              f"Min trace: 0.08mm (3mil), min spacing: 0.08mm (3mil), min drill: 0.2mm (8mil). "              f"Rule violations will now show as DRC markers in the board editor.")         ),

@@ -65,7 +65,7 @@ <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 2-Layer design rules+<description language="en">3rd party fab 2-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -78,8 +78,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 2-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 2-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 2-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -88,8 +88,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -65,7 +65,7 @@ <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -84,8 +84,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -94,8 +94,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -20,7 +20,7 @@ adom-desktop fusion_load_design_rules '{}'                       # what is loade adom-desktop fusion_set_design_rules  '{"preset":"adom"}'        # apply Adom's DRU ``` -Adom's DRU rules ship with the bridge under `resources/`. Applying a house ruleset before routing is+The bundled DRU rules ship with the bridge under `resources/`. Applying a fab ruleset before routing is what keeps a board manufacturable at the fab you use.  ## Layers

@@ -2692,7 +2692,7 @@         "pack": "dict {fab, vendor, process, layers, file, record}"       },       "statusVerb": null,-      "summary": "Load a FAB's design rules (DRC) into the open board. The rule packs live on the wiki page adom/pcb-design-rules (JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB and Adom InstaPCB; one .edru per vendor/process/layer count, every number citing the vendor's own capabilities page): the bridge fetches the pack, stages it on the box, and the add-in runs `drc load`. {action:'list'} answers with every (fab, process, layers) row so you can offer the user a real choice; no fab means the bundled Adom InstaPCB rules for the board's layer count (what ab's removed fusion_apply_instapcb_rules did); druPath loads an .edru already on the Fusion machine; druText/druBase64 loads one that exists only on your side. Layers auto-detects from the open board. ALWAYS confirm with fusion_alerts afterwards: a refused file is an in-canvas toast, never a dialog.",+      "summary": "Load a FAB's design rules (DRC) into the open board. The rule packs live on the wiki page adom/pcb-design-rules (JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB and the 3rd party fab; one .edru per vendor/process/layer count, every number citing the vendor's own capabilities page): the bridge fetches the pack, stages it on the box, and the add-in runs `drc load`. {action:'list'} answers with every (fab, process, layers) row so you can offer the user a real choice; no fab means the bundled 3rd party fab rules for the board's layer count; druPath loads an .edru already on the Fusion machine; druText/druBase64 loads one that exists only on your side. Layers auto-detects from the open board. ALWAYS confirm with fusion_alerts afterwards: a refused file is an in-canvas toast, never a dialog.",       "timeoutSeconds": 90     },     {

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" /> <param name="dpMaxLengthDifference" value="10mm" /> <param name="dpGapFactor" value="2.5" />-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" /> <param name="dpMaxLengthDifference" value="10mm" /> <param name="dpGapFactor" value="2.5" />-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -1695,7 +1695,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -1714,8 +1714,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -1724,8 +1724,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" /> <param name="dpMaxLengthDifference" value="10mm" /> <param name="dpGapFactor" value="2.5" />-<description language="en">Adom InstaPCB 4-Layer design rules+<description language="en">3rd party fab 4-Layer design rules  Board thickness: 1.6mm Copper weight: 1oz (35um)@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)  Vias:-- Min 0.15mm via allowed on 4-layer now with InstaPCB-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter  Drill:@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.  Annular Ring:-Vias: 0.1mm annular ring is InstaPCB min-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min+Vias: 0.1mm annular ring is the 3rd party fab min+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min However, they prefer 0.25mm annular ring or above  </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -297,7 +297,7 @@ _T = [      {"outputPath": "optional str", "grouped": "optional bool (default true)"}, {"componentCount": "int", "grouped": "bool"}, 60, None, False, {"outputPath": "C:/tmp/bom.csv"}),     ("fusion_export_cpl", "Export the Component Placement List (pick-and-place) CSV.",      {"outputPath": "optional str", "side": "optional str (all|top|bottom)"}, {"topCount": "int", "bottomCount": "int"}, 60, None, False, {"outputPath": "C:/tmp/cpl.csv"}),-    ("fusion_set_design_rules", "Load a FAB's design rules (DRC) into the open board. The rule packs live on the wiki page adom/pcb-design-rules (JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB and Adom InstaPCB; one .edru per vendor/process/layer count, every number citing the vendor's own capabilities page): the bridge fetches the pack, stages it on the box, and the add-in runs `drc load`. {action:'list'} answers with every (fab, process, layers) row so you can offer the user a real choice; no fab means the bundled Adom InstaPCB rules for the board's layer count (what ab's removed fusion_apply_instapcb_rules did); druPath loads an .edru already on the Fusion machine; druText/druBase64 loads one that exists only on your side. Layers auto-detects from the open board. ALWAYS confirm with fusion_alerts afterwards: a refused file is an in-canvas toast, never a dialog.",+    ("fusion_set_design_rules", "Load a FAB's design rules (DRC) into the open board. The rule packs live on the wiki page adom/pcb-design-rules (JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB and the 3rd party fab; one .edru per vendor/process/layer count, every number citing the vendor's own capabilities page): the bridge fetches the pack, stages it on the box, and the add-in runs `drc load`. {action:'list'} answers with every (fab, process, layers) row so you can offer the user a real choice; no fab means the bundled 3rd party fab rules for the board's layer count; druPath loads an .edru already on the Fusion machine; druText/druBase64 loads one that exists only on your side. Layers auto-detects from the open board. ALWAYS confirm with fusion_alerts afterwards: a refused file is an in-canvas toast, never a dialog.",      {"fab": "optional str vendorSlug (jlcpcb|pcbway|osh-park|seeed-fusion|eurocircuits|aisler|elecrow|advanced-circuits-4pcb|sierra-circuits|macrofab|nextpcb|allpcb|adom-instapcb)", "process": "optional str (the vendor's tier: standard|advanced|proto|enig|hasl|...; default standard)", "layers": "optional str (auto|2|4|6)", "druPath": "optional str .edru/.dru ALREADY on the Fusion machine, loaded as-is", "druText": "optional str: the whole .edru/.dru file as text, for rules that exist only on YOUR side (a container). The bridge stages it on the box and loads it (1.10.37; replaces ab's removed fusion_load_design_rules)", "druBase64": "optional str: the same, base64-encoded", "druName": "optional str: file name for the staged copy", "action": "optional str (apply|list|export|show)"}, {"activeWorkspace": "str", "description": "str", "pack": "dict {fab, vendor, process, layers, file, record}"}, 90, None, False, {"fab": "jlcpcb", "layers": "2"}),     ("fusion_detect_layers", "Detect 2-layer vs 4-layer board (ULP + CAM comparison).",      {}, {"layerCount": "int", "copperLayers": "[int]"}, 90, None, False, {}),

@@ -18,7 +18,7 @@ Opening the `.brd` child directly gives an isolated view. See [schematics](schem ```bash adom-bridge fusion_set_design_rules '{"action":"list"}'                              # every fab, process, layers row adom-bridge fusion_set_design_rules '{"fab":"jlcpcb","process":"standard","layers":"2"}'-adom-bridge fusion_set_design_rules '{}'                                             # the bundled Adom InstaPCB rules+adom-bridge fusion_set_design_rules '{}'                                             # the bundled 3rd party fab rules adom-bridge fusion_set_design_rules '{"druPath":"C:/tmp/house.edru"}'                # a local rule file, as-is adom-bridge fusion_alerts '{}'                                                       # confirm the load ```@@ -26,14 +26,14 @@ adom-bridge fusion_alerts '{}' `fusion_set_design_rules` loads a fab's rules into the open board. The rule packs live on the wiki page [adom/pcb-design-rules](https://wiki.adom.inc/adom/pcb-design-rules): JLCPCB, PCBWay, OSH Park, Seeed, Eurocircuits, Aisler, Elecrow, Advanced Circuits, Sierra, MacroFab, NextPCB, ALLPCB-and Adom InstaPCB, one `.edru` per vendor, process and layer count, every number citing the+and the 3rd party fab, one `.edru` per vendor, process and layer count, every number citing the vendor's own capabilities page. The bridge fetches the pack, stages it on the box, and the add-in runs `drc load`. `layers` auto-detects from the open board. `{action:"list"}` answers on a machine without Fusion, so you can offer the user a real choice of fab before a board is open. `apply` and `export` need a board open and say so themselves.  Read `ruleWarnings` in the reply. The bridge scans the downloaded profile and warns when it carries-a same-signal Copper Clearance rule over an all/all or trace scope. The InstaPCB 2L profile, like+a same-signal Copper Clearance rule over an all/all or trace scope. The 3rd party fab 2L profile, like the other generated profiles, carries "Same-net track spacing" (0.25 mm, all/all, samesignal=yes). On the six-net test fixture native DRC reported that one rule as 31 Overlap warnings, at the 13 pad entries and 18 trace and via joints. With the rule disabled the identical board is clean. Use

@@ -1,6 +1,6 @@ {   "slug": "fusion-bridge",-  "version": "1.11.9",+  "version": "1.11.10",   "type": "app",   "description": "This package installs the bridge's SKILLS into your container so your AI knows how to drive it; Adom Bridge loads the bridge runtime itself from the release zip.",   "dependencies": {

@@ -1,6 +1,6 @@ {   "slug": "fusion-bridge",-  "version": "1.11.9",+  "version": "1.11.10",   "type": "app",   "description": "This package installs the bridge's SKILLS into your container so your AI knows how to drive it; Adom Bridge loads the bridge runtime itself from the release zip.",   "dependencies": {

@@ -253,7 +253,7 @@ pub fn set_design_rules(ctx: &Ctx, args: &Value, pass: &dyn Fn(&str, Value) -> V     }     let mut rule_warnings: Vec<Value> = Vec::new();     if action == "list" {-        let idx = match design_rules_index(&ctx.state_dir) { Ok(i) => i, Err(e) => return json!({"success": false, "errorCode": "design_rules_page_unreachable", "error": e.chars().take(200).collect::<String>(), "_hint": "The wiki page adom/pcb-design-rules did not answer; the bundled Adom InstaPCB rules still apply with no fab argument."}) };+        let idx = match design_rules_index(&ctx.state_dir) { Ok(i) => i, Err(e) => return json!({"success": false, "errorCode": "design_rules_page_unreachable", "error": e.chars().take(200).collect::<String>(), "_hint": "The wiki page adom/pcb-design-rules did not answer; the bundled 3rd party fab rules still apply with no fab argument."}) };         let rows: Vec<Value> = idx["vendors"].as_array().cloned().unwrap_or_default().iter().map(|v| json!({"fab": v["vendorSlug"], "vendor": v["vendor"], "process": v["process"], "layers": v["layerCount"], "available": v["filesGenerated"].as_bool().unwrap_or(false)})).collect();         return json!({"success": true, "rules": rows, "count": rows.len(), "page": "https://wiki.adom.inc/adom/pcb-design-rules", "_hint": "Pick a row and call fusion_set_design_rules {fab, process, layers}. Layers auto-detects when omitted (2 or 4 from the open board)."});     }@@ -263,7 +263,7 @@ pub fn set_design_rules(ctx: &Ctx, args: &Value, pass: &dyn Fn(&str, Value) -> V         let mut layers = match &a["layers"] { Value::Null => "auto".to_string(), v => crate::fusion_prefs::py_str(v) };         if layers == "auto" { let det = pass("detect_layers", json!({})); layers = det["data"]["layerCount"].as_i64().or(det["layerCount"].as_i64()).unwrap_or(2).to_string(); }         let layers_n: i64 = layers.parse().unwrap_or(2);-        let idx = match design_rules_index(&ctx.state_dir) { Ok(i) => i, Err(e) => return json!({"success": false, "errorCode": "design_rules_page_unreachable", "error": e.chars().take(200).collect::<String>(), "_hint": "Could not fetch the rule packs from wiki.adom.inc; pass druPath to a local .edru, or omit fab for the bundled Adom InstaPCB rules."}) };+        let idx = match design_rules_index(&ctx.state_dir) { Ok(i) => i, Err(e) => return json!({"success": false, "errorCode": "design_rules_page_unreachable", "error": e.chars().take(200).collect::<String>(), "_hint": "Could not fetch the rule packs from wiki.adom.inc; pass druPath to a local .edru, or omit fab for the bundled 3rd party fab rules."}) };         let row = match design_rules_pick(&idx, &fab, a["process"].as_str().unwrap_or(""), layers_n) { Ok(r) => r, Err(alt) => return json!({"success": false, "errorCode": "design_rules_not_found", "fab": fab, "layers": layers_n, "available": alt, "_hint": "No pack for that fab/process/layer count; `available` lists what the page has. fusion_set_design_rules {action:'list'} shows every row."}) };         if row["filesGenerated"].as_bool() != Some(true) { return json!({"success": false, "errorCode": "design_rules_not_generated", "fab": fab, "process": row["process"], "layers": layers_n, "_hint": "The page has this vendor's record but no generated .edru yet (the vendor publishes no usable limits for it). Pick another process or fab."}); }         let rel = row["files"]["fusionEdru"].as_str().unwrap_or("").to_string();

@@ -14697,7 +14697,7 @@ def _design_rules_index(max_age_s: int = 3600) -> dict:  def _design_rules_pick(idx: dict, fab: str, process: str, layers: int):     """The index row for (fab, process, layers). fab matches vendorSlug or a loose alias-    (jlcpcb, pcbway, instapcb, oshpark...); process defaults to the vendor's standard tier."""+    (jlcpcb, pcbway, oshpark...); process defaults to the vendor's standard tier."""     want = re.sub(r"[^a-z0-9]", "", (fab or "").lower())     rows = [v for v in idx.get("vendors") or [] if re.sub(r"[^a-z0-9]", "", v.get("vendorSlug", "").lower()) == want             or want and want in re.sub(r"[^a-z0-9]", "", v.get("vendorSlug", "").lower())]@@ -14716,8 +14716,8 @@ def _handle_set_design_rules(fusion_info: dict, args: dict) -> dict:     rules into the open board. The rule packs live on the wiki page adom/pcb-design-rules     (one JSON record per vendor/process/layer count, generated .edru per row, every number     citing the vendor's own capabilities page); the bridge fetches the .edru, stages it on-    the box, and the add-in runs `drc load <path>`. No fab (or fab:"instapcb" with the page-    unreachable) keeps the bundled Adom InstaPCB behaviour. action:"list" answers with the+    the box, and the add-in runs `drc load <path>`. No fab (or the bundled fab with the page+    unreachable) keeps the bundled 3rd party fab behaviour. action:"list" answers with the     vendors, processes and layer counts on the page so the AI can offer a real choice.      AI hint: the pack is per (vendor, process, layers). "jlcpcb" alone means its standard@@ -14734,13 +14734,13 @@ def _handle_set_design_rules(fusion_info: dict, args: dict) -> dict:             idx = _design_rules_index()         except Exception as e:             return {"success": False, "errorCode": "design_rules_page_unreachable", "error": str(e)[:200],-                    "_hint": "The wiki page adom/pcb-design-rules did not answer; the bundled Adom InstaPCB rules still apply with no fab argument."}+                    "_hint": "The wiki page adom/pcb-design-rules did not answer; the bundled 3rd party fab rules still apply with no fab argument."}         rows = [{"fab": v.get("vendorSlug"), "vendor": v.get("vendor"), "process": v.get("process"),                  "layers": v.get("layerCount"), "available": bool(v.get("filesGenerated"))} for v in idx.get("vendors") or []]         return {"success": True, "rules": rows, "count": len(rows), "page": "https://wiki.adom.inc/adom/pcb-design-rules",                 "_hint": "Pick a row and call fusion_set_design_rules {fab, process, layers}. Layers auto-detects when omitted (2 or 4 from the open board)."}     if action in ("show", "export") or (not fab and not dru_path):-        return _proxy_to_addin("set_design_rules", a, timeout=90)   # the bundled InstaPCB path, unchanged+        return _proxy_to_addin("set_design_rules", a, timeout=90)   # the bundled 3rd party fab path, unchanged     if not dru_path:         layers = str(a.get("layers") or "auto")         if layers == "auto":@@ -14750,7 +14750,7 @@ def _handle_set_design_rules(fusion_info: dict, args: dict) -> dict:             idx = _design_rules_index()         except Exception as e:             return {"success": False, "errorCode": "design_rules_page_unreachable", "error": str(e)[:200],-                    "_hint": "Could not fetch the rule packs from wiki.adom.inc; pass druPath to a local .edru, or omit fab for the bundled Adom InstaPCB rules."}+                    "_hint": "Could not fetch the rule packs from wiki.adom.inc; pass druPath to a local .edru, or omit fab for the bundled 3rd party fab rules."}         row, alt = _design_rules_pick(idx, fab, a.get("process") or "", int(layers))         if not row:             return {"success": False, "errorCode": "design_rules_not_found", "fab": fab, "layers": int(layers),

@@ -136,7 +136,7 @@ fusion_set_design_rules {"action": "list"}                       // every (fab, fusion_set_design_rules {"fab": "jlcpcb", "layers": "2"}         // standard tier; layers auto-detects when omitted fusion_set_design_rules {"fab": "pcbway", "process": "advanced", "layers": "4"} fusion_set_design_rules {"druPath": "C:/Users/me/my-fab.edru"}   // a local file, as-is-fusion_set_design_rules {}                                       // the bundled Adom InstaPCB rules (unchanged)+fusion_set_design_rules {}                                       // the bundled 3rd party fab rules (unchanged) ```  Read `ruleWarnings` in the apply reply (1.10.3+): it names any rule in the downloaded profile