Fusion - the Fusion 360 Bridge

@@ -10093,6 +10093,8 @@ def _mtp_generate(lib_name, ex, part_name, urn="", rex=None, r_urn="", solo=True     # is R1, so a resistor-under-test becomes R2.     pfx = (ex.get("prefix") or "U").strip() or "U"     part_ref = (pfx + "2") if (pfx.upper() == "R" and not solo) else (pfx + "1")+    # FR4 sized from the package's FULL drawing (silk, docu, courtyard), never a fixed box+    _geo = _test_board_geometry(ex["package"], margin=3.0, with_resistor=not solo)     if solo:         # SOLO layout (John, 2026-08-16: "when demoing a single component, you don't need         # extra components... it's just confusing"): JUST the part - one symbol on the@@ -10113,11 +10115,7 @@ def _mtp_generate(lib_name, ex, part_name, urn="", rex=None, r_urn="", solo=True          '<instance part="' + part_ref + '" gate="' + ex["gateName"] + '" x="25.4" y="12.7"/>'          '</instances><busses/><nets/></sheet></sheets></schematic></drawing></eagle>\n')         brd = (_MTP_HEAD + ex["layers"] +-         '<board><plain>'-         '<wire x1="0" y1="0" x2="8" y2="0" width="0.2" layer="20"/>'-         '<wire x1="8" y1="0" x2="8" y2="6" width="0.2" layer="20"/>'-         '<wire x1="8" y1="6" x2="0" y2="6" width="0.2" layer="20"/>'-         '<wire x1="0" y1="6" x2="0" y2="0" width="0.2" layer="20"/></plain>'+         '<board><plain>' + _test_board_outline(_geo["w"], _geo["h"]) + '</plain>'          '<libraries><library name="' + lib_name + '"><packages>' + ex["package"] + '</packages>'          + (('<packages3d><package3d name="' + part_name + '" urn="" wip_urn="' + urn + '" locally_modified="yes" type="model">'              '<packageinstances><packageinstance name="' + ex["pkgName"] + '"/></packageinstances>'@@ -10125,7 +10123,7 @@ def _mtp_generate(lib_name, ex, part_name, urn="", rex=None, r_urn="", solo=True          + '</library></libraries>'          '<attributes/><variantdefs/><classes><class number="0" name="default" width="0" drill="0"/></classes>'          '<designrules name="default"/><autorouter/>'-         '<elements><element name="' + part_ref + '" library="' + lib_name + '" package="' + ex["pkgName"] + '" value="" x="4" y="3"'+         '<elements><element name="' + part_ref + '" library="' + lib_name + '" package="' + ex["pkgName"] + '" value="" x="' + str(_geo["px"]) + '" y="' + str(_geo["py"]) + '"'          + ((' package3d_urn="' + urn + '"') if urn else '') + '/></elements>'          '<signals/></board></drawing></eagle>\n')         return sch, brd@@ -10153,30 +10151,82 @@ def _mtp_generate(lib_name, ex, part_name, urn="", rex=None, r_urn="", solo=True      '<pinref part="' + part_ref + '" gate="' + g + '" pin="' + p2 + '"/></segment></net>'      '</nets></sheet></sheets></schematic></drawing></eagle>\n')     brd = (_MTP_HEAD + ex["layers"] +-     '<board><plain>'-     '<wire x1="0" y1="0" x2="14" y2="0" width="0.2" layer="20"/>'-     '<wire x1="14" y1="0" x2="14" y2="9" width="0.2" layer="20"/>'-     '<wire x1="14" y1="9" x2="0" y2="9" width="0.2" layer="20"/>'-     '<wire x1="0" y1="9" x2="0" y2="0" width="0.2" layer="20"/></plain>'+     '<board><plain>' + _test_board_outline(_geo["w"], _geo["h"]) + '</plain>'      '<libraries>' + lib.replace('<symbols>' + ex["symbol"] + '</symbols><devicesets>' + ex["deviceset"] + '</devicesets>', '')      + rlib.replace('<symbols>' + (rex["symbol"] if rex else _MTP_R_SYM) + '</symbols><devicesets>' + (rex["deviceset"] if rex else _MTP_R_DS) + '</devicesets>', '')      + '</libraries>'      '<attributes/><variantdefs/><classes><class number="0" name="default" width="0" drill="0"/></classes>'      '<designrules name="default"/><autorouter/>'      '<elements>'-     '<element name="R1" library="' + r_lib_name + '" package="' + r_pkg_name + '" value="330" x="3.5" y="4.5"'+     '<element name="R1" library="' + r_lib_name + '" package="' + r_pkg_name + '" value="330" x="' + str(_geo["rx"]) + '" y="' + str(_geo["ry"]) + '"'      + ((' package3d_urn="' + r_urn + '"') if (rex and r_urn) else '') + '/>'-     '<element name="' + part_ref + '" library="' + lib_name + '" package="' + ex["pkgName"] + '" value="" x="9.5" y="4.5"'+     '<element name="' + part_ref + '" library="' + lib_name + '" package="' + ex["pkgName"] + '" value="" x="' + str(_geo["px"]) + '" y="' + str(_geo["py"]) + '"'      + ((' package3d_urn="' + urn + '"') if urn else '') + '/>'      '</elements><signals>'      '<signal name="N1"><contactref element="R1" pad="' + r_pads[r_pin2] + '"/><contactref element="' + part_ref + '" pad="' + pads[p1] + '"/>'-     '<wire x1="4.35" y1="4.5" x2="8.5" y2="4.5" width="0.3" layer="1"/></signal>'+     + ('<wire x1="%s" y1="%s" x2="%s" y2="%s" width="0.3" layer="1"/></signal>' % _geo["wire"]) +      '<signal name="VCC"><contactref element="R1" pad="' + r_pads[r_pin1] + '"/></signal>'      '<signal name="GND"><contactref element="' + part_ref + '" pad="' + pads[p2] + '"/></signal>'      '</signals></board></drawing></eagle>\n')     return sch, brd  +def _pkg_extent_mm(package_xml: str):+    """(minx, miny, maxx, maxy) of EVERYTHING a package draws: pads, smds, wires, circles,+    rectangles, polygons and text on ANY layer (silkscreen, docu, courtyard included). The+    test board's FR4 must enclose all of it (John, 2026-08-30: "make the fr4 big enough so i+    can see the whole silkscreen ... pin 1 indicators")."""+    import re as _re+    xs, ys = [], []+    try:+        for m in _re.finditer(r'<smd [^>]*x="([-0-9.]+)" y="([-0-9.]+)" dx="([-0-9.]+)" dy="([-0-9.]+)"', package_xml):+            x, y, dx, dy = map(float, m.groups())+            r = max(dx, dy) / 2.0   # rotation-safe+            xs += [x - r, x + r]; ys += [y - r, y + r]+        for m in _re.finditer(r'<pad [^>]*x="([-0-9.]+)" y="([-0-9.]+)"[^>]*?(?:diameter="([-0-9.]+)")?', package_xml):+            x, y = float(m.group(1)), float(m.group(2)); r = (float(m.group(3)) if m.group(3) else 1.0) / 2.0+            xs += [x - r, x + r]; ys += [y - r, y + r]+        for m in _re.finditer(r'<wire x1="([-0-9.]+)" y1="([-0-9.]+)" x2="([-0-9.]+)" y2="([-0-9.]+)" width="([-0-9.]+)"', package_xml):+            x1, y1, x2, y2, w = map(float, m.groups())+            xs += [x1 - w, x1 + w, x2 - w, x2 + w]; ys += [y1 - w, y1 + w, y2 - w, y2 + w]+        for m in _re.finditer(r'<circle x="([-0-9.]+)" y="([-0-9.]+)" radius="([-0-9.]+)" width="([-0-9.]+)"', package_xml):+            x, y, r, w = map(float, m.groups()); r += w+            xs += [x - r, x + r]; ys += [y - r, y + r]+        for m in _re.finditer(r'<rectangle x1="([-0-9.]+)" y1="([-0-9.]+)" x2="([-0-9.]+)" y2="([-0-9.]+)"', package_xml):+            x1, y1, x2, y2 = map(float, m.groups()); xs += [x1, x2]; ys += [y1, y2]+        for m in _re.finditer(r'<vertex x="([-0-9.]+)" y="([-0-9.]+)"', package_xml):+            xs.append(float(m.group(1))); ys.append(float(m.group(2)))+        # >NAME / >VALUE labels are movable and sit outside the part; they do not size the board.+    except Exception:+        pass+    if not xs or not ys:+        return (-3.0, -3.0, 3.0, 3.0)+    return (min(xs), min(ys), max(xs), max(ys))+++def _test_board_geometry(package_xml: str, margin: float = 3.0, with_resistor: bool = False) -> dict:+    """Board outline + element positions so the whole package (silk, docu, courtyard) sits on+    FR4 with `margin` mm around it; the series resistor, when present, gets its own bay on the+    left. Returns {w, h, px, py, rx, ry, wire}."""+    x0, y0, x1, y1 = _pkg_extent_mm(package_xml)+    pw, ph = (x1 - x0), (y1 - y0)+    bay = 7.0 if with_resistor else 0.0        # room for a 0603 + its own margin+    w = round(bay + pw + 2 * margin, 2)+    h = round(max(ph + 2 * margin, 9.0 if with_resistor else 0.0), 2)+    px = round(bay + margin - x0, 3)           # element origin so its minx lands at bay+margin+    py = round(h / 2.0 - (y0 + y1) / 2.0, 3)   # vertically centred+    rx, ry = 3.5, round(h / 2.0, 3)+    return {"w": w, "h": h, "px": px, "py": py, "rx": rx, "ry": ry,+            "wire": (rx + 0.85, ry, round(px + x0 - 0.3, 3), ry), "extent": [x0, y0, x1, y1]}+++def _test_board_outline(w: float, h: float) -> str:+    return ('<wire x1="0" y1="0" x2="%s" y2="0" width="0.2" layer="20"/>'+            '<wire x1="%s" y1="0" x2="%s" y2="%s" width="0.2" layer="20"/>'+            '<wire x1="%s" y1="%s" x2="0" y2="%s" width="0.2" layer="20"/>'+            '<wire x1="0" y1="%s" x2="0" y2="0" width="0.2" layer="20"/>' % (w, w, w, h, w, h, h, h))++ _TEST_PROJECT: dict = {} try:    # restore the last generated test project so the DESIGN surfaces (project/schematic/         # 2d/3d) survive a bridge respawn - an install used to wipe this and those four verbs