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Generalize Fusion routing skill for electrical and thermal board engineering

John Lauer ·4532e36764 ·1mo ago ·parent d6fd89d
3 files changed +164−100
skills/fusion-routing/SKILL.md+86−100
@@ -1,104 +1,90 @@ --- name: fusion-routing-description: Use when asked to route a net, draw traces, add vias, pour copper or reproduce the Astra routing demos live in Fusion with fusion_routing_state, fusion_route_net, fusion_routing_drc and fusion_plan_route. Two-layer geometric preflight, native Autodesk DRC before and after, manufacturer rules loaded from adom/pcb-design-rules first. Trigger words - route this net, draw a trace, add a via, copper pour, refill, ratsnest, airwires, DRC, design rules, JLCPCB rules, reproduce the routing demo.+description: >-+  Route and review PCB copper in Autodesk Fusion through Fusion Bridge. Use for trace paths,+  vias, manufacturer design rules, power and ground connections, copper pours, thermal+  spreading and copper-ablation layouts. Inspect the actual board and verify native copper,+  connectivity and DRC. Applies to ordinary board work, independently of recording or demos. --- -Parent skill: [fusion-bridge](../../SKILL.md).--Read `fusion_routing_state {expectDocument}` and keep its `boardId` and `revision`.-Use an isolated test board until this development feature is promoted. Existing-user designs and pinned runtimes must be preserved.--Call `fusion_route_net` with the exact `expectDocument`, `boardId`,-`expectedRevision`, `net`, and `points` or `paths`. Coordinates/widths are mm;-copper layers are 1 and 16. Use `{pad:"J1.1"}` for pad coordinates or-`{x:14,y:17,layer:16}` to change outgoing layer with a through via.--`dryRun:true` checks all geometry without adding copper. Geometric preflight is-conservative and incomplete; it refuses unsupported boards. Every actual call-verifies the copper delta by a new Fusion export. Inspect semantic `success`,-`verified`, and `mutationAttempted`. A timeout or mismatch is not authorization-to replay. Commands are not an atomic Undo group.--For live playback, submit one segment/via per call with the consecutive returned-revision. Capture the actual window with `desktop_record_window_start` and-finalize with `desktop_record_window_stop`, including in error paths. Never-replace live copper with a simulated animation. Foreground is opt-in.--Finish with `fusion_routing_drc` using the same identity/revision guards. It-recomputes RATSNEST, runs native Autodesk DRC, and reads all errors including-approved ones. Require `drc.checked`, `drc.clean`, and no remaining nets before-claiming a connected, DRC-clean result. Save/export the final board separately.--See `demo/routing/README.md` for the tested scope, fixture, recorder and evidence.--For the 24-net crossover, see `demo/routing/crossbar/README.md`. Identical-via transitions shared by branches of one request produce one planned via.--For obstacle-aware planning, call `fusion_plan_route` with the same document,-board and revision guards plus `net`, `fromPad`, and `toPad`. It returns a-read-only `plan.route` for `fusion_route_net` and `plan.items` for visible-per-item commits. Grid, via cost, allowVias and bounded node/time limits are-optional. It is a two-pad orthogonal A* planner, not an all-net autorouter.-Use a fresh plan after intervening edits. See `demo/routing/obstacles/README.md`.--## Showing live calculations during a demo--Reuse `AdomActivityPalette`, its branding and close behavior. The repo's-`demo/routing/live_panel.py` serves the shared activity-palette component and SSE-from the container; `prepare_live_panel.py` attaches it to the existing palette.-Show pad endpoints, measured planner output, primitive creation, copper read-back-and native DRC results as they occur. Do not claim every operation has a live UI-unless the caller actually publishes these events. A lost DOM acknowledgment-stops the demo before the next mutation; do not reopen a user-closed palette.--Fusion palettes can be owned popup windows omitted by parent-window capture.-Inspect the popup screenshots and capture its HWND separately if necessary.-Check that both windows are visible, unminimized and large enough before recording.-Preserve raw takes and record synchronization limits when composing two captures.--## Before the first trace: which manufacturer, and whose rules win--Ask the user which board house will build the board before routing anything, unless they-already said. Load that house's rules into the open board and read them back, then keep the-stricter of the rules and the electrical constraints the user states:--```jsonc-fusion_set_design_rules {"action": "list"}                          // the vendors and tiers the wiki page adom/pcb-design-rules carries-fusion_set_design_rules {"fab": "jlcpcb", "layers": "2"}            // the user's answer; process defaults to standard-fusion_set_design_rules {"action": "export", "outputPath": "C:/Users/<you>/Documents/<task>/rules-loaded.edru"}-```--- Read the exported file and quote `mdWireWire` (copper clearance), `msWidth` (minimum width)-  and `msDrill` back to the user before routing; `fusion_alerts {sinceSec:60}` must be empty,-  a refused rule file is an in-canvas toast, not an error.-- Route with `clearance` and `width` no smaller than the loaded rules. A user constraint that-  is stricter (a wider power trace, a larger creepage gap, a keep-out) wins over the vendor-  minimum; the vendor minimum wins over a request to go below it. Say which one you applied.-- `fusion_set_design_rules {}` with no arguments loads the bundled Adom InstaPCB rules. The-  published BQ25792 demos ran on a DIAGNOSTIC copy of those rules (one inherited all-object-  same-net spacing rule disabled on disposable copies); they do not establish compliance with-  the unmodified InstaPCB profile, and neither does a clean `fusion_routing_drc` under any-  profile other than the one the user asked for.--## Checkpoints, and what a save hint is not--Every add-in reply from 1.10.0 carries `documentHygiene` (which open documents need saving)-and, when something does, `_hintDocumentHygiene`. The bridge never saves, closes or discards-on its own. Checkpoint with `fusion_export_eagle_source {outputPath}` (a `.brd` beside your-task folder) or `fusion_save_to_cloud` at milestones and before ending; verify the file exists-and re-read the hint, because an export leaves Fusion's own modified state as it was. Close-only the scratch document this task opened, by its exact name, with-`fusion_close_document {name, save:false}`, after the checkpoint is verified. Never bulk-close.--## Reproducing the published demos from the installed package--The installed package carries these verbs in the bridge runtime and the fixture, plans and-recorders under `demo/routing/` in the page source (`adom-wiki repo clone adom/fusion-bridge`).-`demo/routing/README.md` is the fixture walkthrough; `demo/routing/bq25792/` holds the BQ25792-plans, replay scripts and audits for the videos on adom/codex. `tools/install-routing-dev.ps1`-is a developer helper for hand-installing an exe over a dev-pinned cache; an installed release-never needs it. Two things are not in this package: the thermal-bottleneck reroute scripts-(video 12, `thermal-reroute/`), whose public source release is still pending on the Codex side,-and the shared EDA skillpack (adom/eda-engineering), which is browseable source, not an-installable package yet. A reproduction that needs them must say so.+# Routing and copper engineering in Fusion++Use the installed `fusion-bridge` skill for desktop discovery and application control.+Discover the live `fusion_describe` contract and check `fusion_readiness` before board calls.+If sign-in blocks readiness, resolve sign-in first; repeating board calls can produce slow,+misleading add-in restart diagnoses. Preserve pinned runtimes and existing user documents.+Work within the user's requested scope and save a recoverable checkpoint before replacing routes.++## Establish fabrication and electrical constraints++Honor a manufacturer/process already selected. Otherwise ask which manufacturer the user+wants, offering profiles returned by `fusion_set_design_rules {action:"list"}`. If undecided,+keep current rules explicitly provisional and continue inspection before dependent routing.++Load the selected fab, process and actual layer count with `fusion_set_design_rules`.+Export the loaded profile and inspect the file, including per-layer/per-object rules and+net classes. Compare rules by name and meaning, not file order or a successful command reply.+Legacy EAGLE keys such as `mdWireWire`, `msWidth` and `msDrill` do not describe every native+EDRU rule. Check native alerts for a rejected load. Keep the stricter applicable fabrication+and user/electrical constraints. A process's minimum isolation channel is not a universal+high-voltage clearance; derive insulation constraints from the actual environment and voltage.++Read [electrical priorities](references/electrical-priorities.md) for power paths, sensitive+signals, clean bends and via choices. Read [copper and thermal design](references/copper-thermal.md)+when assigning pours, retaining copper for ablation, or improving heat spreading.++## Select the supported routing path++Read `fusion_routing_state {expectDocument}` and retain its exact `boardId` and `revision`.+`fusion_route_net` requires these plus the exact net and points/paths. Coordinates and widths+are millimeters. Use pad references for endpoints where supported. Layer-changing waypoints+create through vias according to the live contract.++The conservative `fusion_route_net` preflight and bounded `fusion_plan_route` planner support+two-layer boards. The planner is a two-pad orthogonal A* search, not an all-net autorouter.+Do not feed it a four-layer power board or imply it enforces all electrical constraints.+For supported two-layer work, dry-run proposed geometry, inspect its electrical suitability,+then commit with the same guards. Replan after intervening changes.++For inner layers, native pours or other operations outside those verbs, use the documented+`fusion_run_modeling_script` / `fusion_electron_run` extension and the actual board stackup.+Native `LINE`, `VIA`, `POLYGON`, `CHANGE`, `RATSNEST` and `SHOW` are electronics commands,+not invented bridge verbs. These paths need their own identity checks, clearance analysis,+native readback and DRC; they do not inherit the dedicated routing verb's preflight guarantees.+Never transplant a worked example's layer numbers, dimensions or net names without inspection.++## Commit, inspect, and recover++Inspect semantic `success`, `verified`, `mutationAttempted`, returned copper and revision.+Use the next returned revision for the next edit. Operations are not an atomic Undo group.+On timeout or mismatch, inspect the board before deciding whether any operation needs retrying.++On affected Fusion builds a completed net can raise Autodesk's unexpected-condition modal.+If the reply carries `fusionUnexpectedCondition` or a classified `fusion_unexpected_condition`,+treat it as an application fault with possibly committed copper. Verify actual connectivity+and geometry, checkpoint, and inspect remaining alerts before continuing. Do not count modal+dismissal alone as a verified route or blindly repeat the final segment.++Use the existing Adom activity palette for useful progress when requested; respect its close+state and the user's foreground preference. Recording, narration and fixture replay are optional+presentation tasks, not prerequisites for routing a board.++## Validate and save++Refill copper before measuring connectivity. Run native DRC before and after with the same+selected rules, reporting inherited and new violations separately. `fusion_routing_drc` reads+approved errors as well; require `drc.checked`, clean applicable rules and no remaining+connections before calling the result connected and DRC-clean. A diagnostic rule profile+is not certification under the manufacturer's full profile. Check schematic parity/ERC and+power, thermal and signal-integrity requirements separately where relevant.++Inspect `documentHygiene` / `_hintDocumentHygiene`. Export a verified checkpoint with+`fusion_export_eagle_source` or save through the documented native/cloud workflow. Verify+output existence and usable contents. Exporting a file does not necessarily clear Fusion's+modified state. Close only completed task-owned scratch documents by exact name after verifying+the checkpoint; do not bulk-close or discard original user work.++Summarize actual changes, rule provenance, connectivity/DRC results, saved artifacts and remaining+engineering assumptions. Optional board-specific examples live under `demo/routing/` in the+Fusion Bridge wiki source; no example, video, Codex package or particular AI provider is required+to apply this skill.
skills/fusion-routing/references/copper-thermal.mdadded+47
@@ -0,0 +1,47 @@+# Pours, copper retention, and thermal paths++Before allocating copper, inventory hot/high-current devices, exposed pads, thermal holes and+existing heatsink vias. Resolve each pad's electrical net from the board and datasheet: a MOSFET's+large thermal pad is not necessarily ground. Establish loss estimates or label thermal comparisons+as illustrative when losses and enclosure conditions are unknown.++Reserve broad connected copper from thermal pads and useful plated connections, balancing routing+space, assembly and other devices' cooling. Outer-layer spreading can help surface heat rejection;+inner routing can free it, subject to the actual stackup and return planes. Set native polygon net,+layer, rank, clearance, relief and orphan settings explicitly. Refill and inspect fragmentation,+thermals and contact to load pads. A large outline or zero airwires can conceal a thin residual+trace carrying the current. Use disposable diagnostics to establish whether the pour itself+provides the intended electrical path; preserve the accepted board.++After initial routing, expand useful connected regions into permissible remaining area. Measure+refilled copper unions excluding drill holes; do not double-count overlap or floating islands as+connected heatsinking. Account for copper reassigned from ground or another thermal path. Report+coverage and useful net area separately; larger area is not automatically better overall cooling.++Inspect narrow necks and traces that nearly divide a region. If a distant lobe is poorly coupled,+consider rerouting an appropriate obstructing signal, using another layer and existing plated+endpoints or justified new vias. Preserve signal references, width and other constraints. Compare+connectivity, DRC, route length, ground continuity and heat flow before accepting the move. A failed+candidate is discarded, not silently substituted into the reported final plan.++For ablation, maximize retained copper only when that is the user's fabrication objective.+Electrical insulation, edge clearance and keepouts remain binding. Retain floating islands only+when requested and suitable for the circuit/process; do not count them as net-connected heat+paths or default to them for every board. Coverage alone does not establish laser-cycle savings:+contour length, travel and required passes also matter.++For mask choices, compare coating conduction resistance, convection and radiation. Removing mask+adds negligible macroscopic area; low-emissivity bright metal can radiate less than coated copper.+Use actual finish data or a labeled sensitivity range. Treat partial openings spatially or label+an area-weighted approximation. Contact heatsinks/chassis paths require separate electrical+isolation, interface and assembly design. Do not assume exposing copper always improves cooling.++For calculated heat spreading, state source temperature or power boundary, ambient, copper+thickness/conductivity, convection, emissivity, mask properties and included layers. Check mesh+sensitivity, energy balance and neck behavior. Distinguish bottom-sheet heat-flow estimates from+junction temperature, complete-board dissipation and measured results. Include package/via/FR4,+other layers and enclosure effects when the decision requires them; otherwise disclose omissions.++After accepted changes, native-refill and rerun the same rule profile, save the analyzed geometry,+and highlight the actual affected nets when explaining the result. Report tradeoffs and remaining+qualification work instead of calling an illustrative candidate globally optimal.
skills/fusion-routing/references/electrical-priorities.mdadded+31
@@ -0,0 +1,31 @@+# Electrical priorities and route shape++Start from the actual netlist, component datasheets, stackup, copper thickness, load cases and+board constraints. Ask only for missing information that affects the requested routing decision.+Do not infer current from a net name or a wide-looking existing trace.++Inventory supply/return paths, high-current connectors, switching loops, gate drives, sense+connections, clocks and differential signals. Preserve placements the user did not authorize+changing. Budget voltage drop and resistive loss using path length, cross-section and copper+resistivity at an appropriate temperature. Current capacity also depends on layer, copper weight,+allowed rise, adjacent copper, vias and enclosure; use applicable primary guidance and state+assumptions rather than declaring a current rating from width alone.++Prefer horizontal/vertical paths with 45-degree transitions where routing freedom permits.+Minimize unnecessary corners, acute wedges and tiny segments. Check angles after native readback,+including pad escapes; allow a justified exception when electrical or footprint geometry requires+it. Curves are an option when requested and supported, with controlled radius and native geometry+verification. Aesthetic cleanup must not lengthen critical loops or break impedance constraints.++Reserve compact switching-current loops and an adjacent return path before ordinary signals.+Keep switch-node copper only as large as electrically/thermally justified; do not expand every+power-labeled net indiscriminately. Keep sense lines away from switching copper and route Kelvin+connections to their intended sensing points. Differential impedance, pair spacing, skew and+reference continuity follow the actual interface specification and stackup.++Select via drills, annular rings and counts for fabrication, current, heat and assembly. Include+via barrels in voltage-drop/thermal estimates; do not assume an arbitrary via count shares current+equally. Reuse electrically valid plated endpoints when practical. For every layer change, inspect+the reference plane and return transition. Report longer routes, removed ground copper and other+costs of an alternate path. Reject a relocation that improves appearance or heat spreading while+violating the signal's electrical constraints.