component
FT602Q-B-T
Public Made by Adomby adom
FTDI USB ICs, QFN-76(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+156docs/ft602q-b-t-datasheet.pdfdocs/hero.pngft602q-b-t-etched.glbft602q-b-t-hero.glbft602q-b-t-hero.overlay.json+1769ft602q-b-t.glbft602q-b-t.kicad_mod+859ft602q-b-t.kicad_sym+321ft602q-b-t.lbr+339ft602q-b-t.step+19086package.json+645page.json+651viewers/footprint.html+1viewers/symbol.html+1README.mdadded+156@@ -0,0 +1,156 @@+# FT602Q-B-T++**FTDI** · USB ICs · QFN-76(9x9)++FT602Q-B-T from FTDI, in a QFN-76(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground. |+| 2 | AVDD | power_in | +1.0V power input for the PLL (0.9 to 1.1V operating, can be fed from DV10). |+| 3 | VD10 | power_in | +1.0V core voltage input. |+| 4 | BE_0 | bidirectional | Parallel FIFO bus byte enable I/O bit 0. |+| 5 | BE_1 | bidirectional | Parallel FIFO bus byte enable I/O bit 1. |+| 6 | BE_2 | bidirectional | Parallel FIFO bus byte enable I/O bit 2. |+| 7 | BE_3 | bidirectional | Parallel FIFO bus byte enable I/O bit 3. |+| 8 | TXE_N | output | In 245 Synchronous FIFO mode, transmit FIFO empty output (write only when logic 0); in Multi-Channel FIFO mode, optional Status Valid output. |+| 9 | RXF_N | output | In 245 Synchronous FIFO mode add external pull up in normal operation; in Multi-Channel FIFO mode, Data Receive Acknowledge output. |+| 10 | RESERVED1 | input | Reserved; add external pull up in normal operation. |+| 11 | WR_N | input | Active-low Write Enable input in 245 Synchronous FIFO mode; Data Transaction Request input in Multi-Channel FIFO mode. |+| 12 | RESERVED2 | input | Add external pull up in normal operation. |+| 13 | RESERVED3 | input | Add external pull up in normal operation. |+| 14 | VCCIO | power_in | Power input for the I/O block, supports +2.5/+3.3V. |+| 15 | RESET_N | input | Chip reset input, active low. |+| 16 | INT_N | input | Interrupt input, active low; used for I2C interrupt request or to wake the device from sleep. |+| 17 | SCL | bidirectional | I2C serial clock line (open drain). |+| 18 | SDA | bidirectional | I2C serial data line (open drain). |+| 19 | RESERVED4 | unconnected | Reserved; do not connect. |+| 20 | VCC33 | power_in | +3.3V power input for chip and internal LDO. |+| 21 | XI | input | Crystal input for the internal oscillator (30MHz crystal recommended). |+| 22 | XO | output | Crystal output for the internal oscillator. |+| 23 | DP | bidirectional | Hi-speed USB differential transceiver (positive). |+| 24 | VCC33 | power_in | +3.3V power input for chip and internal LDO. |+| 25 | DM | bidirectional | Hi-speed USB differential transceiver (negative). |+| 26 | GND | power_in | Ground. |+| 27 | RREF | passive | PHY reference resistor pin; connect a 1.6k ohm 1% resistor to ground to provide reference voltage to the USB2 PHY. |+| 28 | VDDA | power_in | +3.3V power input for the USB2.0 and USB3.0 PHYs. |+| 29 | GND | power_in | Ground. |+| 30 | VD10 | power_in | +1.0V core voltage input. |+| 31 | TODN | output | Super Speed USB transmitter differential pair (negative). |+| 32 | TODP | output | Super Speed USB transmitter differential pair (positive). |+| 33 | VD10 | power_in | +1.0V core voltage input. |+| 34 | RIDN | input | Super Speed USB receiver differential pair (negative). |+| 35 | RIDP | input | Super Speed USB receiver differential pair (positive). |+| 36 | GND | power_in | Ground. |+| 37 | VBUS | power_in | USB bus power detect pin; input voltage should be greater than 2.7V. |+| 38 | VCC33 | power_in | +3.3V power input for chip and internal LDO. |+| 39 | DV10 | power_out | +1.0V output from internal LDO; connect to VD10 and AVDD with a 4.7uF capacitor to ground recommended. |+| 40 | DATA_0 | input | Parallel FIFO bus data input bit 0. |+| 41 | DATA_1 | input | Parallel FIFO bus data input bit 1. |+| 42 | DATA_2 | input | Parallel FIFO bus data input bit 2. |+| 43 | DATA_3 | input | Parallel FIFO bus data input bit 3. |+| 44 | DATA_4 | input | Parallel FIFO bus data input bit 4. |+| 45 | DATA_5 | input | Parallel FIFO bus data input bit 5. |+| 46 | DATA_6 | input | Parallel FIFO bus data input bit 6. |+| 47 | DATA_7 | input | Parallel FIFO bus data input bit 7. |+| 48 | VD10 | power_in | +1.0V core voltage input. |+| 49 | VCCIO | power_in | Power input for the I/O block, supports +2.5/+3.3V. |+| 50 | DATA_8 | bidirectional | Parallel FIFO bus data I/O bit 8. |+| 51 | DATA_9 | bidirectional | Parallel FIFO bus data I/O bit 9. |+| 52 | DATA_10 | bidirectional | Parallel FIFO bus data I/O bit 10. |+| 53 | DATA_11 | bidirectional | Parallel FIFO bus data I/O bit 11. |+| 54 | DATA_12 | bidirectional | Parallel FIFO bus data I/O bit 12. |+| 55 | DATA_13 | bidirectional | Parallel FIFO bus data I/O bit 13. |+| 56 | DATA_14 | bidirectional | Parallel FIFO bus data I/O bit 14. |+| 57 | DATA_15 | bidirectional | Parallel FIFO bus data I/O bit 15. |+| 58 | CLK | output | Parallel FIFO bus clock output to the FIFO bus master, configurable as 66MHz or 100MHz for both FIFO bus modes. |+| 59 | VCCIO | power_in | Power input for the I/O block, supports +2.5/+3.3V. |+| 60 | DATA_16 | input | Parallel FIFO bus data input bit 16. |+| 61 | DATA_17 | input | Parallel FIFO bus data input bit 17. |+| 62 | DATA_18 | input | Parallel FIFO bus data input bit 18. |+| 63 | DATA_19 | input | Parallel FIFO bus data input bit 19. |+| 64 | DATA_20 | input | Parallel FIFO bus data input bit 20. |+| 65 | DATA_21 | input | Parallel FIFO bus data input bit 21. |+| 66 | DATA_22 | input | Parallel FIFO bus data input bit 22. |+| 67 | DATA_23 | input | Parallel FIFO bus data input bit 23. |+| 68 | VCCIO | power_in | Power input for the I/O block, supports +2.5/+3.3V. |+| 69 | DATA_24 | input | Parallel FIFO bus data input bit 24. |+| 70 | DATA_25 | input | Parallel FIFO bus data input bit 25. |+| 71 | DATA_26 | input | Parallel FIFO bus data input bit 26. |+| 72 | DATA_27 | input | Parallel FIFO bus data input bit 27. |+| 73 | DATA_28 | input | Parallel FIFO bus data input bit 28. |+| 74 | DATA_29 | input | Parallel FIFO bus data input bit 29. |+| 75 | DATA_30 | input | Parallel FIFO bus data input bit 30. |+| 76 | DATA_31 | input | Parallel FIFO bus data input bit 31. |+| 77 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | FTDI |+| Package | QFN-76(9x9) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 77 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Storage Temperature | | -65 | | 150 | °C | | 15 |+| Ambient Operating Temperature (Power Applied) | | -40 | | 85 | °C | | 15 |+| VCC33/VDDA Supply Voltage | VCC33/VDDA | -0.3 | | 4.6 | V | | 15 |+| VCCIO Supply Voltage | VCCIO | -0.3 | | 4 | V | | 15 |+| VD10 Core Supply Voltage | VD10 | -0.5 | | 1.4 | V | | 15 |+| AVDD PLL Supply Voltage | AVDD | -0.5 | | 1.4 | V | | 15 |+| IOs DC Input Voltage | | -0.5 | | | V | -0.5 to +VCCIO+0.5 V | 15 |+| VCC Operating Supply Voltage | VCC33/VDDA | 3 | 3.3 | 3.6 | V | | 16 |+| VCCIO Operating Supply Voltage | VCCIO_1 | 3 | 3.3 | 3.6 | V | VCCIO=3.3V | 16 |+| VCCIO Operating Supply Voltage | VCCIO_2 | 2.3 | 2.5 | 2.7 | V | VCCIO=2.5V | 16 |+| VCCIO Operating Supply Voltage | VCCIO_3 | 1.65 | 1.8 | 1.95 | V | VCCIO=1.8V | 16 |+| Core/PLL Operating Supply Voltage | VD10/AVDD | 0.9 | 1 | 1.1 | V | | 16 |+| VCCIO Operating Supply Voltage 3.3V | VCCIO_3.3V | 3 | 3.3 | 3.6 | V | Normal Operation | 17 |+| VCCIO Operating Supply Voltage 2.5V | VCCIO_2.5V | 2.3 | 2.5 | 2.7 | V | Normal Operation | 17 |+| VCCIO Operating Supply Voltage 1.8V | VCCIO_1.8V | 1.65 | 1.8 | 1.95 | V | Normal Operation | 17 |+| Input high voltage | VIH | 0.7 | | | xVCCIO | Normal Operation; printed VCCIO*0.7 | 17 |+| Input/output Leakage | Iin/Iout(3.3V) | -10 | | 10 | uA | Without pull-up/down | 17 |+| Input pull-up/pull down resistance | Rpu/Rpd | 30 | 50 | 75 | KΩ | Vout=0~VCCIO | 17 |+| Output drive strength | Iout(VCCIO=3.3V) | 10 | | | mA | Total current | 17 |+| Output drive strength | Iout(VCCIO=2.5V) | 9.4 | | | mA | Total current | 17 |+| Pin Capacitance | Cp | | | 2 | pF | | 17 |+| Slave Drive Data Set Up Time | T1 | 3 | | | ns | | 14 |+| Slave Drive Data Hold Time | T2 | 3.5 | | | ns | | 14 |+| Master Drive Data Set Up Time | T3 | 1 | | | ns | | 14 |+| Master Drive Date Hold Time | T4 | 4.8 | | | ns | | 14 |+| VCC Operating Supply Current | Icc_1 | | 85 | | mA | Idle, SuperSpeed | 16 |+| VCC Operating Supply Current | Icc_2 | | 69 | | mA | Idle, High Speed | 16 |+| VCC Operating Supply Current | Icc_3 | | 185 | | mA | FHD 1080P@60fps Output | 16 |+| VCC Operating Supply Current | Icc_3 | | 4 | | mA | USB Suspend | 16 |+| VCCIO Operating Supply Current | Iccio_1 | | 4.5 | | mA | No data transfer | 16 |+| VCCIO Operating Supply Current | Iccio_2 | | 9.5 | | mA | Data transfer | 16 |+| VCCIO Operating Supply Current | Iccio_3 | | 70 | | μA | USB Suspend | 16 |+| ESD HBM | | | 2 | | kV | JEDEC EIA/JESD22-A114-B, Class 2; printed ±2kV | 15 |+| ESD MM | | | 200 | | V | JEDEC EIA/JESD22-A115-A, Class B; printed ±200V | 15 |+| ESD CDM | | | 500 | | V | JEDEC EIA/JESD22-C101-D, Class-III; printed ±500V | 15 |+| Latch-up | | | 200 | | mA | JESD78, Trigger Class-II; printed ±200mA | 15 |++## CAD (KiCad official)++- Symbol: `FT602Q-B-T`+- Footprint: `Package_DFN_QFN:QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm`+- 3D model: QFN-76(9x9) (KiCad packages3D, STEP)+- 3D model files: `ft602q-b-t-etched.step` / `ft602q-b-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ft602q-b-t.step` / `ft602q-b-t.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [FTDI datasheet](docs/ft602q-b-t-datasheet.pdf) (28 pp, sha256 `1f49dbe70a6ac962`, retrieved 2026-10-30, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ft602q-b-t-datasheet.pdf)
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ft602q-b-t.glbadded⋯ 1 unchanged line ⋯
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symbol="FT602Q-B-T" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm">+ <connects>+ <connect gate="G$1" pin="GND" pad="1"/>+ <connect gate="G$1" pin="AVDD" pad="2"/>+ <connect gate="G$1" pin="VD10" pad="3"/>+ <connect gate="G$1" pin="BE_0" pad="4"/>+ <connect gate="G$1" pin="BE_1" pad="5"/>+ <connect gate="G$1" pin="BE_2" pad="6"/>+ <connect gate="G$1" pin="BE_3" pad="7"/>+ <connect gate="G$1" pin="TXE_N" pad="8"/>+ <connect gate="G$1" pin="RXF_N" pad="9"/>+ <connect gate="G$1" pin="RESERVED1" pad="10"/>+ <connect gate="G$1" pin="WR_N" pad="11"/>+ <connect gate="G$1" pin="RESERVED2" pad="12"/>+ <connect gate="G$1" pin="RESERVED3" pad="13"/>+ <connect gate="G$1" pin="VCCIO" pad="14"/>+ <connect gate="G$1" pin="RESET_N" pad="15"/>+ <connect gate="G$1" pin="INT_N" pad="16"/>+ <connect gate="G$1" pin="SCL" pad="17"/>+ <connect gate="G$1" pin="SDA" pad="18"/>+ <connect gate="G$1" pin="RESERVED4" pad="19"/>+ <connect gate="G$1" pin="VCC33" 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pad="74"/>+ <connect gate="G$1" pin="DATA_28" pad="73"/>+ <connect gate="G$1" pin="DATA_27" pad="72"/>+ <connect gate="G$1" pin="DATA_26" pad="71"/>+ <connect gate="G$1" pin="DATA_25" pad="70"/>+ <connect gate="G$1" pin="DATA_24" pad="69"/>+ <connect gate="G$1" pin="VCCIO@2" pad="68"/>+ <connect gate="G$1" pin="DATA_23" pad="67"/>+ <connect gate="G$1" pin="DATA_22" pad="66"/>+ <connect gate="G$1" pin="DATA_21" pad="65"/>+ <connect gate="G$1" pin="DATA_20" pad="64"/>+ <connect gate="G$1" pin="DATA_19" pad="63"/>+ <connect gate="G$1" pin="DATA_18" pad="62"/>+ <connect gate="G$1" pin="DATA_17" pad="61"/>+ <connect gate="G$1" pin="DATA_16" pad="60"/>+ <connect gate="G$1" pin="VCCIO@3" pad="59"/>+ <connect gate="G$1" pin="CLK" pad="58"/>+ <connect gate="G$1" pin="DATA_15" pad="57"/>+ <connect gate="G$1" pin="DATA_14" pad="56"/>+ <connect gate="G$1" pin="DATA_13" pad="55"/>+ <connect gate="G$1" pin="DATA_12" pad="54"/>+ <connect gate="G$1" pin="DATA_11" pad="53"/>+ <connect gate="G$1" pin="DATA_10" pad="52"/>+ <connect gate="G$1" pin="DATA_9" pad="51"/>+ <connect gate="G$1" pin="DATA_8" pad="50"/>+ <connect gate="G$1" pin="VCCIO@4" pad="49"/>+ <connect gate="G$1" pin="VD10@4" pad="48"/>+ <connect gate="G$1" pin="DATA_7" pad="47"/>+ <connect gate="G$1" pin="DATA_6" pad="46"/>+ <connect gate="G$1" pin="DATA_5" pad="45"/>+ <connect gate="G$1" pin="DATA_4" pad="44"/>+ <connect gate="G$1" pin="DATA_3" pad="43"/>+ <connect gate="G$1" pin="DATA_2" pad="42"/>+ <connect gate="G$1" pin="DATA_1" pad="41"/>+ <connect gate="G$1" pin="DATA_0" pad="40"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
ft602q-b-t.stepadded+19086@@ -0,0 +1,19086 @@+ISO-10303-21;+HEADER;+/* QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2018, kicad StepUp+ * + * This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode), + * with the following exception:+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material', + * then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided + * as part of the 'Licensed Material'.+ * You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement.+ * However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply. + * Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception.+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * *USE 3D CAD DATA AT YOUR OWN RISK*+ * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*+ * + */++FILE_DESCRIPTION(+/* description */ ('model of QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm.step',+/* time_stamp */ '2018-09-14T20:35:25',+/* author */ ('kicad StepUp','ksu'),+/* organization */ ('FreeCAD'),+/* preprocessor_version */ 'OCC',+/* originating_system */ 'kicad StepUp',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN_CC2 { 1 2 10303 214 -1 1 5 4 }'));+ENDSEC;++DATA;+#1 = APPLICATION_PROTOCOL_DEFINITION('committee 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package.jsonadded+645@@ -0,0 +1,645 @@+{+ "slug": "ft602q-b-t",+ "version": "0.1.0",+ "type": "component",+ "description": "FTDI USB ICs, QFN-76(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "ft602q-b-t",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ft602q-b-t.kicad_sym",+ "ft602q-b-t.kicad_mod",+ "ft602q-b-t.glb",+ "ft602q-b-t.step",+ "ft602q-b-t.lbr",+ "docs/hero.png",+ "docs/ft602q-b-t-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ft602q-b-t-hero.glb",+ "ft602q-b-t-hero.overlay.json",+ "ft602q-b-t-etched.glb"+ ],+ "component": {+ "mpn": "FT602Q-B-T",+ "manufacturer": "FTDI",+ "package": "QFN-76(9x9)",+ "pin_count": 77,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "USB ICs",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9d67ba27d9005176975bd38f274f98f4.pdf",+ "parts": {+ "symbol": "ft602q-b-t.kicad_sym",+ "footprint": "ft602q-b-t.kicad_mod",+ "model_3d": "ft602q-b-t-hero.glb",+ "model_3d_plain": "ft602q-b-t-etched.glb",+ "model_3d_step": "ft602q-b-t-etched.step",+ "model_3d_step_plain": "ft602q-b-t.step",+ "lbr": "ft602q-b-t.lbr"+ },+ "distributor_links": {+ "lcsc": "C5742667",+ "digikey": "768-1380-ND",+ "mouser": "895-FT602Q-B-T"+ },+ "distributor_check": {+ "checked_at": "2026-10-30T16:47:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "768-1380-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "895-FT602Q-B-T",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "2",+ "name": "AVDD",+ "type": "power_in",+ "description": "+1.0V power input for the PLL (0.9 to 1.1V operating, can be fed from DV10)."+ },+ {+ "number": "3",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "4",+ "name": "BE_0",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 0."+ },+ {+ "number": "5",+ "name": "BE_1",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 1."+ },+ {+ "number": "6",+ "name": "BE_2",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 2."+ },+ {+ "number": "7",+ "name": "BE_3",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 3."+ },+ {+ "number": "8",+ "name": "TXE_N",+ "type": "output",+ "description": "In 245 Synchronous FIFO mode, transmit FIFO empty output (write only when logic 0); in Multi-Channel FIFO mode, optional Status Valid output."+ },+ {+ "number": "9",+ "name": "RXF_N",+ "type": "output",+ "description": "In 245 Synchronous FIFO mode add external pull up in normal operation; in Multi-Channel FIFO mode, Data Receive Acknowledge output."+ },+ {+ "number": "10",+ "name": "RESERVED1",+ "type": "input",+ "description": "Reserved; add external pull up in normal operation."+ },+ {+ "number": "11",+ "name": "WR_N",+ "type": "input",+ "description": "Active-low Write Enable input in 245 Synchronous FIFO mode; Data Transaction Request input in Multi-Channel FIFO mode."+ },+ {+ "number": "12",+ "name": "RESERVED2",+ "type": "input",+ "description": "Add external pull up in normal operation."+ },+ {+ "number": "13",+ "name": "RESERVED3",+ "type": "input",+ "description": "Add external pull up in normal operation."+ },+ {+ "number": "14",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "15",+ "name": "RESET_N",+ "type": "input",+ "description": "Chip reset input, active low."+ },+ {+ "number": "16",+ "name": "INT_N",+ "type": "input",+ "description": "Interrupt input, active low; used for I2C interrupt request or to wake the device from sleep."+ },+ {+ "number": "17",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C serial clock line (open drain)."+ },+ {+ "number": "18",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C serial data line (open drain)."+ },+ {+ "number": "19",+ "name": "RESERVED4",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "20",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "21",+ "name": "XI",+ "type": "input",+ "description": "Crystal input for the internal oscillator (30MHz crystal recommended)."+ },+ {+ "number": "22",+ "name": "XO",+ "type": "output",+ "description": "Crystal output for the internal oscillator."+ },+ {+ "number": "23",+ "name": "DP",+ "type": "bidirectional",+ "description": "Hi-speed USB differential transceiver (positive)."+ },+ {+ "number": "24",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "25",+ "name": "DM",+ "type": "bidirectional",+ "description": "Hi-speed USB differential transceiver (negative)."+ },+ {+ "number": "26",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "27",+ "name": "RREF",+ "type": "passive",+ "description": "PHY reference resistor pin; connect a 1.6k ohm 1% resistor to ground to provide reference voltage to the USB2 PHY."+ },+ {+ "number": "28",+ "name": "VDDA",+ "type": "power_in",+ "description": "+3.3V power input for the USB2.0 and USB3.0 PHYs."+ },+ {+ "number": "29",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "30",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "31",+ "name": "TODN",+ "type": "output",+ "description": "Super Speed USB transmitter differential pair (negative)."+ },+ {+ "number": "32",+ "name": "TODP",+ "type": "output",+ "description": "Super Speed USB transmitter differential pair (positive)."+ },+ {+ "number": "33",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "34",+ "name": "RIDN",+ "type": "input",+ "description": "Super Speed USB receiver differential pair (negative)."+ },+ {+ "number": "35",+ "name": "RIDP",+ "type": "input",+ "description": "Super Speed USB receiver differential pair (positive)."+ },+ {+ "number": "36",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "37",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB bus power detect pin; input voltage should be greater than 2.7V."+ },+ {+ "number": "38",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "39",+ "name": "DV10",+ "type": "power_out",+ "description": "+1.0V output from internal LDO; connect to VD10 and AVDD with a 4.7uF capacitor to ground recommended."+ },+ {+ "number": "40",+ "name": "DATA_0",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 0."+ },+ {+ "number": "41",+ "name": "DATA_1",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 1."+ },+ {+ "number": "42",+ "name": "DATA_2",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 2."+ },+ {+ "number": "43",+ "name": "DATA_3",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 3."+ },+ {+ "number": "44",+ "name": "DATA_4",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 4."+ },+ {+ "number": "45",+ "name": "DATA_5",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 5."+ },+ {+ "number": "46",+ "name": "DATA_6",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 6."+ },+ {+ "number": "47",+ "name": "DATA_7",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 7."+ },+ {+ "number": "48",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "49",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "50",+ "name": "DATA_8",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 8."+ },+ {+ "number": "51",+ "name": "DATA_9",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 9."+ },+ {+ "number": "52",+ "name": "DATA_10",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 10."+ },+ {+ "number": "53",+ "name": "DATA_11",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 11."+ },+ {+ "number": "54",+ "name": "DATA_12",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 12."+ },+ {+ "number": "55",+ "name": "DATA_13",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 13."+ },+ {+ "number": "56",+ "name": "DATA_14",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 14."+ },+ {+ "number": "57",+ "name": "DATA_15",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 15."+ },+ {+ "number": "58",+ "name": "CLK",+ "type": "output",+ "description": "Parallel FIFO bus clock output to the FIFO bus master, configurable as 66MHz or 100MHz for both FIFO bus modes."+ },+ {+ "number": "59",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "60",+ "name": "DATA_16",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 16."+ },+ {+ "number": "61",+ "name": "DATA_17",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 17."+ },+ {+ "number": "62",+ "name": "DATA_18",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 18."+ },+ {+ "number": "63",+ "name": "DATA_19",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 19."+ },+ {+ "number": "64",+ "name": "DATA_20",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 20."+ },+ {+ "number": "65",+ "name": "DATA_21",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 21."+ },+ {+ "number": "66",+ "name": "DATA_22",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 22."+ },+ {+ "number": "67",+ "name": "DATA_23",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 23."+ },+ {+ "number": "68",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "69",+ "name": "DATA_24",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 24."+ },+ {+ "number": "70",+ "name": "DATA_25",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 25."+ },+ {+ "number": "71",+ "name": "DATA_26",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 26."+ },+ {+ "number": "72",+ "name": "DATA_27",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 27."+ },+ {+ "number": "73",+ "name": "DATA_28",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 28."+ },+ {+ "number": "74",+ "name": "DATA_29",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 29."+ },+ {+ "number": "75",+ "name": "DATA_30",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 30."+ },+ {+ "number": "76",+ "name": "DATA_31",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 31."+ },+ {+ "number": "77",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The centre exposed pad is internally connected to GND (page 22) but has no pin number in the datashe; The datasheet tables the VCCIO pins as 2.5/3.3V, but other sections and the DC table also allow 1.8V; RREF is listed as an input in the datasheet. I set it to passive because it connects to an external ",+ "2/77 pins cited to the wrong page (name found elsewhere): ['38:VCC33@p9', '59:VCCIO@p9']",+ "1/77 pin names appear NOWHERE in the datasheet text: ['22:XO@p8']"+ ],+ "pages_sent": 28,+ "cost_usd": 0.2363,+ "at": "2026-10-30T16:46:59"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9d67ba27d9005176975bd38f274f98f4.pdf",+ "pages": 28,+ "sha256": "1f49dbe70a6ac962",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 77,+ "described": 77,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ft602q-b-t.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9.0,+ 9.0,+ 0.87+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "3ab1064cae4fe9fd862cf68d892e572981a8eef91ec6d357d43dd753058ee5b3",+ "checked": "2026-10-30",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ft602q-b-t-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9.0,+ 9.0,+ 0.87+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "abdc07146a5dd9edeececa95ce33eac7adbd926969c45e0645ac2838f6c5da86",+ "checked": "2026-10-30",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "QFN-76",+ "source_page": 22,+ "D": {+ "nom_mm": 9.0,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 9.0,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.4,+ "range_mm": [+ null,+ null+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "ft602q-b-t.step",+ "verdict": "SKIP",+ "reasons": [+ "the datasheet dimensions give no height or body size to compare"+ ],+ "by": "factory/package_fit.py"+ }+ }+ }+}
page.jsonadded+651@@ -0,0 +1,651 @@+{+ "slug": "ft602q-b-t",+ "version": "0.1.0",+ "type": "component",+ "description": "FTDI USB ICs, QFN-76(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "ft602q-b-t",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ft602q-b-t.kicad_sym",+ "ft602q-b-t.kicad_mod",+ "ft602q-b-t.glb",+ "ft602q-b-t.step",+ "ft602q-b-t.lbr",+ "docs/hero.png",+ "docs/ft602q-b-t-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ft602q-b-t-hero.glb",+ "ft602q-b-t-hero.overlay.json",+ "ft602q-b-t-etched.glb"+ ],+ "component": {+ "mpn": "FT602Q-B-T",+ "manufacturer": "FTDI",+ "package": "QFN-76(9x9)",+ "pin_count": 77,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "USB ICs",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9d67ba27d9005176975bd38f274f98f4.pdf",+ "parts": {+ "symbol": "ft602q-b-t.kicad_sym",+ "footprint": "ft602q-b-t.kicad_mod",+ "model_3d": "ft602q-b-t-hero.glb",+ "model_3d_plain": "ft602q-b-t-etched.glb",+ "model_3d_step": "ft602q-b-t-etched.step",+ "model_3d_step_plain": "ft602q-b-t.step",+ "lbr": "ft602q-b-t.lbr"+ },+ "distributor_links": {+ "lcsc": "C5742667",+ "digikey": "768-1380-ND",+ "mouser": "895-FT602Q-B-T"+ },+ "distributor_check": {+ "checked_at": "2026-10-30T16:47:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "768-1380-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "895-FT602Q-B-T",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "2",+ "name": "AVDD",+ "type": "power_in",+ "description": "+1.0V power input for the PLL (0.9 to 1.1V operating, can be fed from DV10)."+ },+ {+ "number": "3",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "4",+ "name": "BE_0",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 0."+ },+ {+ "number": "5",+ "name": "BE_1",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 1."+ },+ {+ "number": "6",+ "name": "BE_2",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 2."+ },+ {+ "number": "7",+ "name": "BE_3",+ "type": "bidirectional",+ "description": "Parallel FIFO bus byte enable I/O bit 3."+ },+ {+ "number": "8",+ "name": "TXE_N",+ "type": "output",+ "description": "In 245 Synchronous FIFO mode, transmit FIFO empty output (write only when logic 0); in Multi-Channel FIFO mode, optional Status Valid output."+ },+ {+ "number": "9",+ "name": "RXF_N",+ "type": "output",+ "description": "In 245 Synchronous FIFO mode add external pull up in normal operation; in Multi-Channel FIFO mode, Data Receive Acknowledge output."+ },+ {+ "number": "10",+ "name": "RESERVED1",+ "type": "input",+ "description": "Reserved; add external pull up in normal operation."+ },+ {+ "number": "11",+ "name": "WR_N",+ "type": "input",+ "description": "Active-low Write Enable input in 245 Synchronous FIFO mode; Data Transaction Request input in Multi-Channel FIFO mode."+ },+ {+ "number": "12",+ "name": "RESERVED2",+ "type": "input",+ "description": "Add external pull up in normal operation."+ },+ {+ "number": "13",+ "name": "RESERVED3",+ "type": "input",+ "description": "Add external pull up in normal operation."+ },+ {+ "number": "14",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "15",+ "name": "RESET_N",+ "type": "input",+ "description": "Chip reset input, active low."+ },+ {+ "number": "16",+ "name": "INT_N",+ "type": "input",+ "description": "Interrupt input, active low; used for I2C interrupt request or to wake the device from sleep."+ },+ {+ "number": "17",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C serial clock line (open drain)."+ },+ {+ "number": "18",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C serial data line (open drain)."+ },+ {+ "number": "19",+ "name": "RESERVED4",+ "type": "unconnected",+ "description": "Reserved; do not connect."+ },+ {+ "number": "20",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "21",+ "name": "XI",+ "type": "input",+ "description": "Crystal input for the internal oscillator (30MHz crystal recommended)."+ },+ {+ "number": "22",+ "name": "XO",+ "type": "output",+ "description": "Crystal output for the internal oscillator."+ },+ {+ "number": "23",+ "name": "DP",+ "type": "bidirectional",+ "description": "Hi-speed USB differential transceiver (positive)."+ },+ {+ "number": "24",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "25",+ "name": "DM",+ "type": "bidirectional",+ "description": "Hi-speed USB differential transceiver (negative)."+ },+ {+ "number": "26",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "27",+ "name": "RREF",+ "type": "passive",+ "description": "PHY reference resistor pin; connect a 1.6k ohm 1% resistor to ground to provide reference voltage to the USB2 PHY."+ },+ {+ "number": "28",+ "name": "VDDA",+ "type": "power_in",+ "description": "+3.3V power input for the USB2.0 and USB3.0 PHYs."+ },+ {+ "number": "29",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "30",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "31",+ "name": "TODN",+ "type": "output",+ "description": "Super Speed USB transmitter differential pair (negative)."+ },+ {+ "number": "32",+ "name": "TODP",+ "type": "output",+ "description": "Super Speed USB transmitter differential pair (positive)."+ },+ {+ "number": "33",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "34",+ "name": "RIDN",+ "type": "input",+ "description": "Super Speed USB receiver differential pair (negative)."+ },+ {+ "number": "35",+ "name": "RIDP",+ "type": "input",+ "description": "Super Speed USB receiver differential pair (positive)."+ },+ {+ "number": "36",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "37",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB bus power detect pin; input voltage should be greater than 2.7V."+ },+ {+ "number": "38",+ "name": "VCC33",+ "type": "power_in",+ "description": "+3.3V power input for chip and internal LDO."+ },+ {+ "number": "39",+ "name": "DV10",+ "type": "power_out",+ "description": "+1.0V output from internal LDO; connect to VD10 and AVDD with a 4.7uF capacitor to ground recommended."+ },+ {+ "number": "40",+ "name": "DATA_0",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 0."+ },+ {+ "number": "41",+ "name": "DATA_1",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 1."+ },+ {+ "number": "42",+ "name": "DATA_2",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 2."+ },+ {+ "number": "43",+ "name": "DATA_3",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 3."+ },+ {+ "number": "44",+ "name": "DATA_4",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 4."+ },+ {+ "number": "45",+ "name": "DATA_5",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 5."+ },+ {+ "number": "46",+ "name": "DATA_6",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 6."+ },+ {+ "number": "47",+ "name": "DATA_7",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 7."+ },+ {+ "number": "48",+ "name": "VD10",+ "type": "power_in",+ "description": "+1.0V core voltage input."+ },+ {+ "number": "49",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "50",+ "name": "DATA_8",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 8."+ },+ {+ "number": "51",+ "name": "DATA_9",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 9."+ },+ {+ "number": "52",+ "name": "DATA_10",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 10."+ },+ {+ "number": "53",+ "name": "DATA_11",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 11."+ },+ {+ "number": "54",+ "name": "DATA_12",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 12."+ },+ {+ "number": "55",+ "name": "DATA_13",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 13."+ },+ {+ "number": "56",+ "name": "DATA_14",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 14."+ },+ {+ "number": "57",+ "name": "DATA_15",+ "type": "bidirectional",+ "description": "Parallel FIFO bus data I/O bit 15."+ },+ {+ "number": "58",+ "name": "CLK",+ "type": "output",+ "description": "Parallel FIFO bus clock output to the FIFO bus master, configurable as 66MHz or 100MHz for both FIFO bus modes."+ },+ {+ "number": "59",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "60",+ "name": "DATA_16",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 16."+ },+ {+ "number": "61",+ "name": "DATA_17",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 17."+ },+ {+ "number": "62",+ "name": "DATA_18",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 18."+ },+ {+ "number": "63",+ "name": "DATA_19",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 19."+ },+ {+ "number": "64",+ "name": "DATA_20",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 20."+ },+ {+ "number": "65",+ "name": "DATA_21",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 21."+ },+ {+ "number": "66",+ "name": "DATA_22",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 22."+ },+ {+ "number": "67",+ "name": "DATA_23",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 23."+ },+ {+ "number": "68",+ "name": "VCCIO",+ "type": "power_in",+ "description": "Power input for the I/O block, supports +2.5/+3.3V."+ },+ {+ "number": "69",+ "name": "DATA_24",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 24."+ },+ {+ "number": "70",+ "name": "DATA_25",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 25."+ },+ {+ "number": "71",+ "name": "DATA_26",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 26."+ },+ {+ "number": "72",+ "name": "DATA_27",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 27."+ },+ {+ "number": "73",+ "name": "DATA_28",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 28."+ },+ {+ "number": "74",+ "name": "DATA_29",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 29."+ },+ {+ "number": "75",+ "name": "DATA_30",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 30."+ },+ {+ "number": "76",+ "name": "DATA_31",+ "type": "input",+ "description": "Parallel FIFO bus data input bit 31."+ },+ {+ "number": "77",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The centre exposed pad is internally connected to GND (page 22) but has no pin number in the datashe; The datasheet tables the VCCIO pins as 2.5/3.3V, but other sections and the DC table also allow 1.8V; RREF is listed as an input in the datasheet. I set it to passive because it connects to an external ",+ "2/77 pins cited to the wrong page (name found elsewhere): ['38:VCC33@p9', '59:VCCIO@p9']",+ "1/77 pin names appear NOWHERE in the datasheet text: ['22:XO@p8']"+ ],+ "pages_sent": 28,+ "cost_usd": 0.2363,+ "at": "2026-10-30T16:46:59"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9d67ba27d9005176975bd38f274f98f4.pdf",+ "pages": 28,+ "sha256": "1f49dbe70a6ac962",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 77,+ "described": 77,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ft602q-b-t.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.87+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ab1064cae4fe9fd862cf68d892e572981a8eef91ec6d357d43dd753058ee5b3",+ "checked": "2026-10-30",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ft602q-b-t-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.87+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "abdc07146a5dd9edeececa95ce33eac7adbd926969c45e0645ac2838f6c5da86",+ "checked": "2026-10-30",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ],+ "package_dims": {+ "package_code": "QFN-76",+ "source_page": 22,+ "D": {+ "nom_mm": 9,+ "range_mm": [+ null,+ null+ ]+ },+ "E1": {+ "nom_mm": 9,+ "range_mm": [+ null,+ null+ ]+ },+ "e": {+ "nom_mm": 0.4,+ "range_mm": [+ null,+ null+ ]+ },+ "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",+ "model_check": {+ "file": "ft602q-b-t.step",+ "verdict": "SKIP",+ "reasons": [+ "the datasheet dimensions give no height or body size to compare"+ ],+ "by": "factory/package_fit.py"+ }+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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viewers/symbol.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>ft602q-b-t</title>