component
F28386DPTPS
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+213@@ -0,0 +1,213 @@+# F28386DPTPS++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)++F28386DPTPS from Texas Instruments, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO10 | bidirectional | General-purpose I/O GPIO10 with peripheral mux options (EPWM6A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 2 | GPIO11 | bidirectional | General-purpose I/O GPIO11 with peripheral mux options (EPWM6B, SCIB_RX, OUTPUTXBAR7, EQEP1_B and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 3 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 4 | GPIO12 | bidirectional | General-purpose I/O GPIO12 with peripheral mux options (EPWM7A, CANB_TX, MDXB, EQEP1_STROBE, SCIC_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 5 | GPIO13 | bidirectional | General-purpose I/O GPIO13 with peripheral mux options (EPWM7B, CANB_RX, MDRB, EQEP1_INDEX, SCIC_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 6 | GPIO14 | bidirectional | General-purpose I/O GPIO14 with peripheral mux options (EPWM8A, SCIB_TX, MCLKXB, OUTPUTXBAR3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 7 | GPIO15 | bidirectional | General-purpose I/O GPIO15 with peripheral mux options (EPWM8B, SCIB_RX, MFSXB, OUTPUTXBAR4 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 8 | GPIO16 | bidirectional | General-purpose I/O GPIO16 with peripheral mux options (SPIA_SIMO, CANB_TX, EPWM9A, SD1_D1, SSIA_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 9 | GPIO17 | bidirectional | General-purpose I/O GPIO17 with peripheral mux options (SPIA_SOMI, CANB_RX, EPWM9B, SD1_C1, SSIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 10 | GPIO18 | bidirectional | General-purpose I/O GPIO18 with peripheral mux options (SPIA_CLK, SCIB_TX, CANA_RX, EPWM10A, EMIF1_CS2n and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 11 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 12 | GPIO19 | bidirectional | General-purpose I/O GPIO19 with peripheral mux options (SPIA_STEn, SCIB_RX, CANA_TX, EPWM10B, EMIF1_CS3n and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 13 | GPIO20 | bidirectional | General-purpose I/O GPIO20 with peripheral mux options (EQEP1_A, MDXA, CANB_TX, EPWM11A, EMIF1_BA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 14 | GPIO21 | bidirectional | General-purpose I/O GPIO21 with peripheral mux options (EQEP1_B, MDRA, CANB_RX, EPWM11B, EMIF1_BA1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 15 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 16 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 17 | GPIO99 | bidirectional | General-purpose I/O GPIO99 with peripheral mux options (EMIF2_A1, EQEP1_INDEX, FSIRXH_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 18 | GPIO8 | bidirectional | General-purpose I/O GPIO8 with peripheral mux options (EPWM5A, CANB_TX, ADCSOCAO, SCIA_TX, MCAN_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 19 | GPIO9 | bidirectional | General-purpose I/O GPIO9 with peripheral mux options (EPWM5B, SCIB_TX, OUTPUTXBAR6, EQEP3_INDEX, SCIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 20 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 21 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 22 | GPIO22 | bidirectional | General-purpose I/O GPIO22 with peripheral mux options (EQEP1_STROBE, MCLKXA, SCIB_TX, EPWM12A, SPIB_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 23 | GPIO23 | bidirectional | General-purpose I/O GPIO23 with peripheral mux options (EQEP1_INDEX, MFSXA, SCIB_RX, EPWM12B, SPIB_STEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 24 | GPIO24 | bidirectional | General-purpose I/O GPIO24 with peripheral mux options (OUTPUTXBAR1, EQEP2_A, MDXB, SPIB_SIMO, PMBUSA_SCL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 25 | GPIO25 | bidirectional | General-purpose I/O GPIO25 with peripheral mux options (OUTPUTXBAR2, EQEP2_B, MDRB, SPIB_SOMI, PMBUSA_SDA and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 26 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 27 | GPIO26 | bidirectional | General-purpose I/O GPIO26 with peripheral mux options (OUTPUTXBAR3, EQEP2_INDEX, MCLKXB, SPIB_CLK, PMBUSA_ALERT and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 28 | GPIO27 | bidirectional | General-purpose I/O GPIO27 with peripheral mux options (OUTPUTXBAR4, EQEP2_STROBE, MFSXB, SPIB_STEn, PMBUSA_CTL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 29 | ADCINC4/CMPIN5P | input | ADC-C input 4 (also comparator 5 positive input CMPIN5P); usable as a general ADC input or for external-reference calibration of all ADCs. |+| 30 | ADCINC3/CMPIN6N | input | ADC-C input 3 (also comparator 6 negative input CMPIN6N). |+| 31 | ADCINC2/CMPIN6P | input | ADC-C input 2 (also comparator 6 positive input CMPIN6P). |+| 32 | VREFLOC | input | ADC-C low reference voltage; connect to VSSA when unused. |+| 33 | VREFLOA | input | ADC-A low reference voltage; connect to VSSA when unused. |+| 34 | VSSA | power_in | Analog ground; connect to VSS if no dedicated analog ground is used. |+| 35 | VREFHIC | input | ADC-C high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIC and VREFLOC, and must not be externally loaded; tie to VDDA when unused. |+| 36 | VDDA | power_in | 3.3V analog supply; place a minimum 2.2µF decoupling capacitor connected to VSSA on each VDDA pin. |+| 37 | VREFHIA | input | ADC-A high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIA and VREFLOA, and must not be externally loaded; tie to VDDA when unused. |+| 38 | ADCINA5/CMPIN2N | input | ADC-A input 5 (also comparator 2 negative input CMPIN2N). |+| 39 | ADCINA4/CMPIN2P | input | ADC-A input 4 (also comparator 2 positive input CMPIN2P). |+| 40 | ADCINA3/CMPIN1N | input | ADC-A input 3 (also comparator 1 negative input CMPIN1N). |+| 41 | ADCINA2/CMPIN1P | input | ADC-A input 2 (also comparator 1 positive input CMPIN1P). |+| 42 | ADCINA1/DACOUTB | passive | ADC-A input 1 or buffered DAC-B output (DACOUTB); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode. |+| 43 | ADCINA0/DACOUTA | passive | ADC-A input 0 or buffered DAC-A output (DACOUTA); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode. |+| 44 | ADCIN14/CMPIN4P | input | Input 14 to all ADCs (also comparator 4 positive input CMPIN4P); usable as a general ADC input or for external-reference calibration of all ADCs. |+| 45 | ADCIN15/CMPIN4N | input | Input 15 to all ADCs (also comparator 4 negative input CMPIN4N); usable as a general ADC input or for external-reference calibration of all ADCs. |+| 46 | ADCINB0/VDAC | passive | ADC-B input 0, or optional external reference VDAC for the on-chip DAC; a 100pF capacitor to VSSA is fixed on this pin, and at least 1µF is required if used as DAC reference. |+| 47 | ADCINB1/DACOUTC | passive | ADC-B input 1 or buffered DAC-C output (DACOUTC); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode. |+| 48 | ADCINB2/CMPIN3P | input | ADC-B input 2 (also comparator 3 positive input CMPIN3P). |+| 49 | ADCINB3/CMPIN3N | input | ADC-B input 3 (also comparator 3 negative input CMPIN3N). |+| 50 | VREFLOB | input | ADC-B low reference voltage; connect to VSSA when unused. |+| 51 | VREFLOD | input | ADC-D low reference voltage; connect to VSSA when unused. |+| 52 | VSSA | power_in | Analog ground; connect to VSS if no dedicated analog ground is used. |+| 53 | VREFHIB | input | ADC-B high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIB and VREFLOB, and must not be externally loaded; tie to VDDA when unused. |+| 54 | VDDA | power_in | 3.3V analog supply; place a minimum 2.2µF decoupling capacitor connected to VSSA on each VDDA pin. |+| 55 | VREFHID | input | ADC-D high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHID and VREFLOD, and must not be externally loaded; tie to VDDA when unused. |+| 56 | ADCIND0/CMPIN7P | input | ADC-D input 0 (also comparator 7 positive input CMPIN7P). |+| 57 | ADCIND1/CMPIN7N | input | ADC-D input 1 (also comparator 7 negative input CMPIN7N). |+| 58 | ADCIND2/CMPIN8P | input | ADC-D input 2 (also comparator 8 positive input CMPIN8P). |+| 59 | ADCIND3/CMPIN8N | input | ADC-D input 3 (also comparator 8 negative input CMPIN8N). |+| 60 | ADCIND4 | input | ADC-D input 4. |+| 61 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 62 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 63 | GPIO30 | bidirectional | General-purpose I/O GPIO30 with peripheral mux options (CANA_RX, EMIF1_CLK, MCAN_RX, EQEP3_STROBE, EPWM16A and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 64 | GPIO28 | bidirectional | General-purpose I/O GPIO28 with peripheral mux options (SCIA_RX, EMIF1_CS4n, OUTPUTXBAR5, EQEP3_A, SD2_D3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 65 | GPIO29 | bidirectional | General-purpose I/O GPIO29 with peripheral mux options (SCIA_TX, EMIF1_SDCKE, OUTPUTXBAR6, EQEP3_B, ESC_SYNC0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 66 | GPIO31 | bidirectional | General-purpose I/O GPIO31 with peripheral mux options (CANA_TX, EMIF1_WEn, MCAN_TX, OUTPUTXBAR8, EQEP3_INDEX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 67 | GPIO32 | bidirectional | General-purpose I/O GPIO32 with peripheral mux options (I2CA_SDA, EMIF1_CS0n, SPIA_SIMO, CLB_OUTPUTXBAR1, EMIF1_OEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 68 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 69 | GPIO33 | bidirectional | General-purpose I/O GPIO33 with peripheral mux options (I2CA_SCL, EMIF1_RNW, SPIA_SOMI, CLB_OUTPUTXBAR2, EMIF1_BA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 70 | GPIO34 | bidirectional | General-purpose I/O GPIO34 with peripheral mux options (OUTPUTXBAR1, EMIF1_CS2n, SPIA_CLK, I2CB_SDA, ENET_MII_CRS and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 71 | GPIO35 | bidirectional | General-purpose I/O GPIO35 with peripheral mux options (SCIA_RX, EMIF1_CS3n, SPIA_STEn, I2CB_SCL, ENET_MII_COL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 72 | VDD3VFL | power_in | 3.3V flash supply pin; place a minimum 0.1µF decoupling capacitor on each VDD3VFL pin. |+| 73 | FLT1 | bidirectional | Flash test pin 1, reserved for TI; must be left unconnected. |+| 74 | FLT2 | bidirectional | Flash test pin 2, reserved for TI; must be left unconnected. |+| 75 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 76 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 77 | TDI | input | JTAG test data input with internal pull-up; data is clocked into the selected register on the rising edge of TCK. |+| 78 | TDO | output | JTAG test data output; contents of the selected register are shifted out on the falling edge of TCK. |+| 79 | TRSTn | input | JTAG test reset with internal pull-down and ~50ns glitch filter; must be held low in normal operation, and an external pull-down of 2.2kΩ to 10kΩ is typically used. |+| 80 | TMS | input | JTAG test mode select with internal pull-up; an external 2.2kΩ pull-up to VDDIO is recommended on the board. |+| 81 | TCK | input | JTAG test clock with internal pull-up. |+| 82 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 83 | GPIO36 | bidirectional | General-purpose I/O GPIO36 with peripheral mux options (SCIA_TX, EMIF1_WAIT, CANA_RX, CLB_OUTPUTXBAR5, EMIF1_A1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 84 | GPIO37 | bidirectional | General-purpose I/O GPIO37 with peripheral mux options (OUTPUTXBAR2, EMIF1_OEn, CANA_TX, CLB_OUTPUTXBAR6, EMIF1_A2 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 85 | GPIO38 | bidirectional | General-purpose I/O GPIO38 with peripheral mux options (EMIF1_A0, SCIC_TX, CANB_TX, CLB_OUTPUTXBAR7, EMIF1_A3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 86 | GPIO39 | bidirectional | General-purpose I/O GPIO39 with peripheral mux options (EMIF1_A1, SCIC_RX, CANB_RX, CLB_OUTPUTXBAR8, EMIF1_A4 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 87 | GPIO40 | bidirectional | General-purpose I/O GPIO40 with peripheral mux options (EMIF1_A2, I2CB_SDA, ENET_MII_CRS, ESC_I2C_SDA and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 88 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 89 | GPIO41 | bidirectional | General-purpose I/O GPIO41 with peripheral mux options (EMIF1_A3, I2CB_SCL, ENET_REVMII_MDIO_RST, ENET_MII_COL, ESC_I2C_SCL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 90 | GPIO48 | bidirectional | General-purpose I/O GPIO48 with peripheral mux options (OUTPUTXBAR3, EMIF1_A8, SCIA_TX, SD1_D1, ENET_PPS1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 91 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 92 | ERRORSTS | output | Error status output; requires an external pull-down resistor when used. |+| 93 | GPIO49 | bidirectional | General-purpose I/O GPIO49 with peripheral mux options (OUTPUTXBAR4, EMIF1_A9, SCIA_RX, SD1_C1, ENET_MII_RX_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 94 | GPIO50 | bidirectional | General-purpose I/O GPIO50 with peripheral mux options (EQEP1_A, EMIF1_A10, SPIC_SIMO, SD1_D2, ENET_MII_RX_DV and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 95 | GPIO51 | bidirectional | General-purpose I/O GPIO51 with peripheral mux options (EQEP1_B, EMIF1_A11, SPIC_SOMI, SD1_C2, ENET_MII_RX_ERR and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 96 | GPIO52 | bidirectional | General-purpose I/O GPIO52 with peripheral mux options (EQEP1_STROBE, EMIF1_A12, SPIC_CLK, SD1_D3, ENET_MII_RX_DATA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 97 | GPIO53 | bidirectional | General-purpose I/O GPIO53 with peripheral mux options (EQEP1_INDEX, EMIF1_D31, EMIF2_D15, SPIC_STEn, SD1_C3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 98 | GPIO54 | bidirectional | General-purpose I/O GPIO54 with peripheral mux options (SPIA_SIMO, EMIF1_D30, EMIF2_D14, EQEP2_A, SCIB_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 99 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 100 | GPIO55 | bidirectional | General-purpose I/O GPIO55 with peripheral mux options (SPIA_SOMI, EMIF1_D29, EMIF2_D13, EQEP2_B, SCIB_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 101 | GPIO56 | bidirectional | General-purpose I/O GPIO56 with peripheral mux options (SPIA_CLK, EMIF1_D28, EMIF2_D12, EQEP2_STROBE, SCIC_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 102 | GPIO57 | bidirectional | General-purpose I/O GPIO57 with peripheral mux options (SPIA_STEn, EMIF1_D27, EMIF2_D11, EQEP2_INDEX, SCIC_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 103 | GPIO58 | bidirectional | General-purpose I/O GPIO58 with peripheral mux options (MCLKRA, EMIF1_D26, EMIF2_D10, OUTPUTXBAR1, SPIB_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 104 | GPIO59 | bidirectional | General-purpose I/O GPIO59 with peripheral mux options (MFSRA, EMIF1_D25, EMIF2_D9, OUTPUTXBAR2, SPIB_STEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 105 | GPIO60 | bidirectional | General-purpose I/O GPIO60 with peripheral mux options (MCLKRB, EMIF1_D24, EMIF2_D8, OUTPUTXBAR3, SPIB_SIMO and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 106 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 107 | GPIO61 | bidirectional | General-purpose I/O GPIO61 with peripheral mux options (MFSRB, EMIF1_D23, EMIF2_D7, OUTPUTXBAR4, SPIB_SOMI and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 108 | GPIO62 | bidirectional | General-purpose I/O GPIO62 with peripheral mux options (SCIC_RX, EMIF1_D22, EMIF2_D6, EQEP3_A, CANA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 109 | GPIO63 | bidirectional | General-purpose I/O GPIO63 with peripheral mux options (SCIC_TX, EMIF1_D21, EMIF2_D5, EQEP3_B, CANA_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 110 | GPIO64 | bidirectional | General-purpose I/O GPIO64 with peripheral mux options (EMIF1_D20, EMIF2_D4, EQEP3_STROBE, SCIA_RX, SSIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 111 | GPIO65 | bidirectional | General-purpose I/O GPIO65 with peripheral mux options (EMIF1_D19, EMIF2_D3, EQEP3_INDEX, SCIA_TX, SSIA_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 112 | GPIO66 | bidirectional | General-purpose I/O GPIO66 with peripheral mux options (EMIF1_D18, EMIF2_D2, I2CB_SDA, SSIA_FSS, ENET_MII_RX_DATA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 113 | GPIO44 | bidirectional | General-purpose I/O GPIO44 with peripheral mux options (EMIF1_A4, ENET_MII_TX_CLK, ESC_TX1_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 114 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 115 | GPIO45 | bidirectional | General-purpose I/O GPIO45 with peripheral mux options (EMIF1_A5, ENET_MII_TX_EN, ESC_TX1_ENA per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 116 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 117 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 118 | GPIO133/AUXCLKIN | bidirectional | General-purpose I/O GPIO133; alternate function AUXCLKIN is the single-ended 3.3V auxiliary clock input for the auxiliary PLL and CPU Timer 2. |+| 119 | NC2 | unconnected | No internal connection; may be left open or tied to VSS or VDDIO, and tying to VDDIO (3.3V) is recommended for PCB compatibility with other C2000 devices. |+| 120 | VDDOSC | power_in | 3.3V supply for the on-chip crystal oscillator (X1/X2) and the two internal zero-pin oscillators; place a minimum 0.1µF decoupling capacitor on each pin. |+| 121 | X2 | output | Crystal oscillator output; connect a quartz crystal circuit between X1 and X2 when using the crystal mode. |+| 122 | VSSOSC | power_in | Crystal oscillator ground; when an external crystal is used, connect to the crystal oscillator circuit ground reference rather than the board ground, otherwise it may be tied to board ground. |+| 123 | X1 | input | Crystal oscillator or single-ended clock input; initialization software must configure this pin before enabling the crystal oscillator, and it can accept a single-ended 3.3V-level clock. |+| 124 | XRSn | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up; a 2.2kΩ to 10kΩ resistor to VDDIO is required, and any noise filter capacitor to VSS must be 100nF or less. |+| 125 | VDDOSC | power_in | 3.3V supply for the on-chip crystal oscillator (X1/X2) and the two internal zero-pin oscillators; place a minimum 0.1µF decoupling capacitor on each pin. |+| 126 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 127 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 128 | GPIO46 | bidirectional | General-purpose I/O GPIO46 with peripheral mux options (EMIF1_A6, SCID_RX, ENET_MII_TX_ERR, ESC_MDIO_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 129 | GPIO47 | bidirectional | General-purpose I/O GPIO47 with peripheral mux options (EMIF1_A7, SCID_TX, ENET_PPS0, ESC_MDIO_DATA per the GPIO mux table); internal pull-up is disabled by default and software-enabled. |+| 130 | GPIO42 | bidirectional | General-purpose I/O GPIO42 with peripheral mux options (I2CA_SDA, ENET_MDIO_CLK, UARTA_TX, SCIA_TX); alternate function USB0DM (USB-0 PHY differential data) when GPBAMSEL[10]=1. |+| 131 | GPIO43 | bidirectional | General-purpose I/O GPIO43 with peripheral mux options (I2CA_SCL, ENET_MDIO_DATA, UARTA_RX, SCIA_RX); alternate function USB0DP (USB-0 PHY differential data) when GPBAMSEL[11]=1. |+| 132 | GPIO67 | bidirectional | General-purpose I/O GPIO67 with peripheral mux options (EMIF1_D17, EMIF2_D1, ENET_MII_RX_CLK, ENET_REVMII_MDIO_RST, SD1_D3); internal pull-up is disabled by default and software-enabled. |+| 133 | GPIO68 | bidirectional | General-purpose I/O GPIO68 with peripheral mux options (EMIF1_D16, EMIF2_D0, ENET_MII_INTR, SD1_C3, ESC_PHY1_LINKSTATUS); internal pull-up is disabled by default and software-enabled. |+| 134 | GPIO69 | bidirectional | General-purpose I/O GPIO69 with peripheral mux options (EMIF1_D15, I2CB_SCL, ENET_MII_TX_EN, ENET_MII_RX_CLK, SD1_D4, SPIC_SIMO); internal pull-up is disabled by default and software-enabled. |+| 135 | GPIO70 | bidirectional | General-purpose I/O GPIO70 with peripheral mux options (EMIF1_D14, CANA_RX, SCIB_TX, MCAN_RX, ENET_MII_RX_DV, SPIC_SOMI); internal pull-up is disabled by default and software-enabled. |+| 136 | GPIO71 | bidirectional | General-purpose I/O GPIO71 with peripheral mux options (EMIF1_D13, CANA_TX, SCIB_RX, MCAN_TX, ENET_MII_RX_DATA0, SPIC_CLK); internal pull-up is disabled by default and software-enabled. |+| 137 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 138 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 139 | GPIO72 | bidirectional | General-purpose I/O GPIO72 with peripheral mux options (EMIF1_D12, CANB_TX, SCIC_TX, ENET_MII_RX_DATA1, ENET_MII_TX_DATA3, SPIC_STEn); internal pull-up is disabled by default and software-enabled. |+| 140 | GPIO73 | bidirectional | General-purpose I/O GPIO73 with peripheral mux options (EMIF1_D11, XCLKOUT, CANB_RX, SCIC_RX, ENET_RMII_CLK, SD2_D2); internal pull-up is disabled by default and software-enabled. |+| 141 | GPIO74 | bidirectional | General-purpose I/O GPIO74 with peripheral mux options (EMIF1_D10, MCAN_TX, ENET_MII_TX_DATA1, SD2_C2, ESC_TX1_DATA1); internal pull-up is disabled by default and software-enabled. |+| 142 | GPIO75 | bidirectional | General-purpose I/O GPIO75 with peripheral mux options (EMIF1_D9, MCAN_RX, ENET_MII_TX_DATA0, SD2_D3, ESC_TX1_DATA0); internal pull-up is disabled by default and software-enabled. |+| 143 | GPIO76 | bidirectional | General-purpose I/O GPIO76 with peripheral mux options (EMIF1_D8, SCID_TX, ENET_MII_RX_ERR, SD2_C3, ESC_PHY_RESETn); internal pull-up is disabled by default and software-enabled. |+| 144 | GPIO77 | bidirectional | General-purpose I/O GPIO77 with peripheral mux options (EMIF1_D7, SCID_RX, SD2_D4, ESC_RX0_CLK); internal pull-up is disabled by default and software-enabled. |+| 145 | GPIO78 | bidirectional | General-purpose I/O GPIO78 with peripheral mux options (EMIF1_D6, EQEP2_A, SD2_C4, ESC_RX0_DV); internal pull-up is disabled by default and software-enabled. |+| 146 | GPIO79 | bidirectional | General-purpose I/O GPIO79 with peripheral mux options (EMIF1_D5, EQEP2_B, SD2_D1, ESC_RX0_ERR); internal pull-up is disabled by default and software-enabled. |+| 147 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 148 | GPIO80 | bidirectional | General-purpose I/O GPIO80 with peripheral mux options (EMIF1_D4, EQEP2_STROBE, SD2_C1, ESC_RX0_DATA0); internal pull-up is disabled by default and software-enabled. |+| 149 | GPIO81 | bidirectional | General-purpose I/O GPIO81 with peripheral mux options (EMIF1_D3, EQEP2_INDEX, ESC_RX0_DATA1); internal pull-up is disabled by default and software-enabled. |+| 150 | GPIO82 | bidirectional | General-purpose I/O GPIO82 with peripheral mux options (EMIF1_D2, ESC_RX0_DATA2); internal pull-up is disabled by default and software-enabled. |+| 151 | GPIO83 | bidirectional | General-purpose I/O GPIO83 with peripheral mux options (EMIF1_D1, ESC_RX0_DATA3); internal pull-up is disabled by default and software-enabled. |+| 152 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 153 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 154 | GPIO84 | bidirectional | General-purpose I/O GPIO84 with peripheral mux options (SCIA_TX, MDXB, UARTA_TX, ESC_TX0_ENA, MDXA); internal pull-up is disabled by default and software-enabled. |+| 155 | GPIO85 | bidirectional | General-purpose I/O GPIO85 with peripheral mux options (EMIF1_D0, SCIA_RX, MDRB, UARTA_RX, ESC_TX0_CLK, MDRA); internal pull-up is disabled by default and software-enabled. |+| 156 | GPIO86 | bidirectional | General-purpose I/O GPIO86 with peripheral mux options (EMIF1_A13, EMIF1_CAS, SCIB_TX, MCLKXB, ESC_PHY0_LINKSTATUS, MCLKXA); internal pull-up is disabled by default and software-enabled. |+| 157 | GPIO87 | bidirectional | General-purpose I/O GPIO87 with peripheral mux options (EMIF1_A14, EMIF1_RAS, SCIB_RX, MFSXB, EMIF1_DQM3, ESC_TX0_DATA0, MFSXA); internal pull-up is disabled by default and software-enabled. |+| 158 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 159 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 160 | GPIO0 | bidirectional | General-purpose I/O GPIO0 with peripheral mux options (EPWM1A, I2CA_SDA, CM-I2CA_SDA, ESC_GPI0, FSITXA_D0); internal pull-up is disabled by default and software-enabled. |+| 161 | GPIO1 | bidirectional | General-purpose I/O GPIO1 with peripheral mux options (EPWM1B, MFSRB, I2CA_SCL, CM-I2CA_SCL, ESC_GPI1, FSITXA_D1); internal pull-up is disabled by default and software-enabled. |+| 162 | GPIO2 | bidirectional | General-purpose I/O GPIO2 with peripheral mux options (EPWM2A, OUTPUTXBAR1, I2CB_SDA, ESC_GPI2, FSITXA_CLK); internal pull-up is disabled by default and software-enabled. |+| 163 | GPIO3 | bidirectional | General-purpose I/O GPIO3 with peripheral mux options (EPWM2B, OUTPUTXBAR2, MCLKRB, I2CB_SCL, ESC_GPI3, FSIRXA_D0); internal pull-up is disabled by default and software-enabled. |+| 164 | GPIO4 | bidirectional | General-purpose I/O GPIO4 with peripheral mux options (EPWM3A, OUTPUTXBAR3, CANA_TX, MCAN_TX, ESC_GPI4, FSIRXA_D1); internal pull-up is disabled by default and software-enabled. |+| 165 | GPIO5 | bidirectional | General-purpose I/O GPIO5 with peripheral mux options (EPWM3B, MFSRA, OUTPUTXBAR3, CANA_RX, MCAN_RX, ESC_GPI5, FSIRXA_CLK); internal pull-up is disabled by default and software-enabled. |+| 166 | GPIO6 | bidirectional | General-purpose I/O GPIO6 with peripheral mux options (EPWM4A, OUTPUTXBAR4, EXTSYNCOUT, EQEP3_A, CANB_TX, ESC_GPI6, FSITXB_D0); internal pull-up is disabled by default and software-enabled. |+| 167 | GPIO7 | bidirectional | General-purpose I/O GPIO7 with peripheral mux options (EPWM4B, MCLKRA, OUTPUTXBAR5, EQEP3_B, CANB_RX, ESC_GPI7, FSITXB_D1); internal pull-up is disabled by default and software-enabled. |+| 168 | VDDIO | power_in | 3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin. |+| 169 | VDD | power_in | 1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS. |+| 170 | GPIO88 | bidirectional | General-purpose I/O GPIO88 with peripheral mux options (EMIF1_A15, EMIF1_DQM0, EMIF1_DQM1, ESC_TX0_DATA1); internal pull-up is disabled by default and software-enabled. |+| 171 | GPIO89 | bidirectional | General-purpose I/O GPIO89 with peripheral mux options (EMIF1_A16, EMIF1_DQM1, SCIC_TX, EMIF1_CAS, ESC_TX0_DATA2); internal pull-up is disabled by default and software-enabled. |+| 172 | GPIO90 | bidirectional | General-purpose I/O GPIO90 with peripheral mux options (EMIF1_A17, EMIF1_DQM2, SCIC_RX, EMIF1_RAS, ESC_TX0_DATA3); internal pull-up is disabled by default and software-enabled. |+| 173 | GPIO91 | bidirectional | General-purpose I/O GPIO91 with peripheral mux options (EMIF1_A18, EMIF1_DQM3, I2CA_SDA, EMIF1_DQM2, PMBUSA_SCL, SSIA_TX, FSIRXF_D0, CLB_OUTPUTXBAR1, SPID_SIMO); internal pull-up is disabled by default and software-enabled. |+| 174 | GPIO92 | bidirectional | General-purpose I/O GPIO92 with peripheral mux options (EMIF1_A19, EMIF1_BA1, I2CA_SCL, EMIF1_DQM0, PMBUSA_SDA, SSIA_RX, FSIRXF_D1, CLB_OUTPUTXBAR2, SPID_SOMI); internal pull-up is disabled by default and software-enabled. |+| 175 | GPIO93 | bidirectional | General-purpose I/O GPIO93 with peripheral mux options (EMIF1_BA0, SCID_TX, PMBUSA_ALERT, SSIA_CLK, FSIRXF_CLK, CLB_OUTPUTXBAR3, SPID_CLK); internal pull-up is disabled by default and software-enabled. |+| 176 | GPIO94 | bidirectional | General-purpose I/O GPIO94 with peripheral mux options (SCID_RX, EMIF1_BA1, PMBUSA_CTL, SSIA_FSS, FSIRXG_D0, CLB_OUTPUTXBAR4, SPID_STEn); internal pull-up is disabled by default and software-enabled. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-176(24x24) |+| Category | Embedded Processors & Controllers |+| Pins | 176 |++## CAD (KiCad official)++- Symbol: `F28386DPTPS`+- Footprint: `Package_QFP:LQFP-176_24x24mm_P0.5mm`+- 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)+- 3D model files: `f28386dptps-etched.step` / `f28386dptps-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `f28386dptps.step` / `f28386dptps.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28384d-q1) (359 pp, sha256 `b16044f781d66c38`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/f28386dptps-datasheet.pdf)
page.jsonadded+1209@@ -0,0 +1,1209 @@+{+ "slug": "f28386dptps",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "f28386dptps",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "f28386dptps.kicad_sym",+ "f28386dptps.kicad_mod",+ "f28386dptps.glb",+ "f28386dptps.step",+ "f28386dptps.lbr",+ "docs/hero.png",+ "docs/f28386dptps-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "f28386dptps-hero.glb",+ "f28386dptps-hero.overlay.json"+ ],+ "component": {+ "mpn": "F28386DPTPS",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-176(24x24)",+ "pin_count": 176,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28384d-q1",+ "parts": {+ "symbol": "f28386dptps.kicad_sym",+ "footprint": "f28386dptps.kicad_mod",+ "model_3d": "f28386dptps-hero.glb",+ "model_3d_plain": "f28386dptps.glb",+ "model_3d_step": "f28386dptps-etched.step",+ "model_3d_step_plain": "f28386dptps.step",+ "lbr": "f28386dptps.lbr"+ },+ "distributor_links": {+ "lcsc": "C3216546",+ "digikey": "296-F28386DPTPS-ND",+ "mouser": "595-F28386DPTPS"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:10:03Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-F28386DPTPS-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-F28386DPTPS",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO10 with peripheral mux options (EPWM6A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "2",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO11 with peripheral mux options (EPWM6B, SCIB_RX, OUTPUTXBAR7, EQEP1_B and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "3",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "4",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO12 with peripheral mux options (EPWM7A, CANB_TX, MDXB, EQEP1_STROBE, SCIC_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "5",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO13 with peripheral mux options (EPWM7B, CANB_RX, MDRB, EQEP1_INDEX, SCIC_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "6",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO14 with peripheral mux options (EPWM8A, SCIB_TX, MCLKXB, OUTPUTXBAR3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "7",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO15 with peripheral mux options (EPWM8B, SCIB_RX, MFSXB, OUTPUTXBAR4 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "8",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO16 with peripheral mux options (SPIA_SIMO, CANB_TX, EPWM9A, SD1_D1, SSIA_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "9",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO17 with peripheral mux options (SPIA_SOMI, CANB_RX, EPWM9B, SD1_C1, SSIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "10",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO18 with peripheral mux options (SPIA_CLK, SCIB_TX, CANA_RX, EPWM10A, EMIF1_CS2n and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "11",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "12",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO19 with peripheral mux options (SPIA_STEn, SCIB_RX, CANA_TX, EPWM10B, EMIF1_CS3n and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "13",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO20 with peripheral mux options (EQEP1_A, MDXA, CANB_TX, EPWM11A, EMIF1_BA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "14",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO21 with peripheral mux options (EQEP1_B, MDRA, CANB_RX, EPWM11B, EMIF1_BA1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "15",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "17",+ "name": "GPIO99",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO99 with peripheral mux options (EMIF2_A1, EQEP1_INDEX, FSIRXH_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "18",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO8 with peripheral mux options (EPWM5A, CANB_TX, ADCSOCAO, SCIA_TX, MCAN_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "19",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO9 with peripheral mux options (EPWM5B, SCIB_TX, OUTPUTXBAR6, EQEP3_INDEX, SCIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "20",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "21",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "22",+ "name": "GPIO22",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO22 with peripheral mux options (EQEP1_STROBE, MCLKXA, SCIB_TX, EPWM12A, SPIB_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "23",+ "name": "GPIO23",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO23 with peripheral mux options (EQEP1_INDEX, MFSXA, SCIB_RX, EPWM12B, SPIB_STEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "24",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO24 with peripheral mux options (OUTPUTXBAR1, EQEP2_A, MDXB, SPIB_SIMO, PMBUSA_SCL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "25",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO25 with peripheral mux options (OUTPUTXBAR2, EQEP2_B, MDRB, SPIB_SOMI, PMBUSA_SDA and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "26",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "27",+ "name": "GPIO26",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO26 with peripheral mux options (OUTPUTXBAR3, EQEP2_INDEX, MCLKXB, SPIB_CLK, PMBUSA_ALERT and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "28",+ "name": "GPIO27",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO27 with peripheral mux options (OUTPUTXBAR4, EQEP2_STROBE, MFSXB, SPIB_STEn, PMBUSA_CTL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "29",+ "name": "ADCINC4/CMPIN5P",+ "type": "input",+ "description": "ADC-C input 4 (also comparator 5 positive input CMPIN5P); usable as a general ADC input or for external-reference calibration of all ADCs."+ },+ {+ "number": "30",+ "name": "ADCINC3/CMPIN6N",+ "type": "input",+ "description": "ADC-C input 3 (also comparator 6 negative input CMPIN6N)."+ },+ {+ "number": "31",+ "name": "ADCINC2/CMPIN6P",+ "type": "input",+ "description": "ADC-C input 2 (also comparator 6 positive input CMPIN6P)."+ },+ {+ "number": "32",+ "name": "VREFLOC",+ "type": "input",+ "description": "ADC-C low reference voltage; connect to VSSA when unused."+ },+ {+ "number": "33",+ "name": "VREFLOA",+ "type": "input",+ "description": "ADC-A low reference voltage; connect to VSSA when unused."+ },+ {+ "number": "34",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground; connect to VSS if no dedicated analog ground is used."+ },+ {+ "number": "35",+ "name": "VREFHIC",+ "type": "input",+ "description": "ADC-C high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIC and VREFLOC, and must not be externally loaded; tie to VDDA when unused."+ },+ {+ "number": "36",+ "name": "VDDA",+ "type": "power_in",+ "description": "3.3V analog supply; place a minimum 2.2µF decoupling capacitor connected to VSSA on each VDDA pin."+ },+ {+ "number": "37",+ "name": "VREFHIA",+ "type": "input",+ "description": "ADC-A high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIA and VREFLOA, and must not be externally loaded; tie to VDDA when unused."+ },+ {+ "number": "38",+ "name": "ADCINA5/CMPIN2N",+ "type": "input",+ "description": "ADC-A input 5 (also comparator 2 negative input CMPIN2N)."+ },+ {+ "number": "39",+ "name": "ADCINA4/CMPIN2P",+ "type": "input",+ "description": "ADC-A input 4 (also comparator 2 positive input CMPIN2P)."+ },+ {+ "number": "40",+ "name": "ADCINA3/CMPIN1N",+ "type": "input",+ "description": "ADC-A input 3 (also comparator 1 negative input CMPIN1N)."+ },+ {+ "number": "41",+ "name": "ADCINA2/CMPIN1P",+ "type": "input",+ "description": "ADC-A input 2 (also comparator 1 positive input CMPIN1P)."+ },+ {+ "number": "42",+ "name": "ADCINA1/DACOUTB",+ "type": "passive",+ "description": "ADC-A input 1 or buffered DAC-B output (DACOUTB); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode."+ },+ {+ "number": "43",+ "name": "ADCINA0/DACOUTA",+ "type": "passive",+ "description": "ADC-A input 0 or buffered DAC-A output (DACOUTA); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode."+ },+ {+ "number": "44",+ "name": "ADCIN14/CMPIN4P",+ "type": "input",+ "description": "Input 14 to all ADCs (also comparator 4 positive input CMPIN4P); usable as a general ADC input or for external-reference calibration of all ADCs."+ },+ {+ "number": "45",+ "name": "ADCIN15/CMPIN4N",+ "type": "input",+ "description": "Input 15 to all ADCs (also comparator 4 negative input CMPIN4N); usable as a general ADC input or for external-reference calibration of all ADCs."+ },+ {+ "number": "46",+ "name": "ADCINB0/VDAC",+ "type": "passive",+ "description": "ADC-B input 0, or optional external reference VDAC for the on-chip DAC; a 100pF capacitor to VSSA is fixed on this pin, and at least 1µF is required if used as DAC reference."+ },+ {+ "number": "47",+ "name": "ADCINB1/DACOUTC",+ "type": "passive",+ "description": "ADC-B input 1 or buffered DAC-C output (DACOUTC); has a 50kΩ internal pull-down that cannot be disabled in ADC input or DAC output mode."+ },+ {+ "number": "48",+ "name": "ADCINB2/CMPIN3P",+ "type": "input",+ "description": "ADC-B input 2 (also comparator 3 positive input CMPIN3P)."+ },+ {+ "number": "49",+ "name": "ADCINB3/CMPIN3N",+ "type": "input",+ "description": "ADC-B input 3 (also comparator 3 negative input CMPIN3N)."+ },+ {+ "number": "50",+ "name": "VREFLOB",+ "type": "input",+ "description": "ADC-B low reference voltage; connect to VSSA when unused."+ },+ {+ "number": "51",+ "name": "VREFLOD",+ "type": "input",+ "description": "ADC-D low reference voltage; connect to VSSA when unused."+ },+ {+ "number": "52",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground; connect to VSS if no dedicated analog ground is used."+ },+ {+ "number": "53",+ "name": "VREFHIB",+ "type": "input",+ "description": "ADC-B high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHIB and VREFLOB, and must not be externally loaded; tie to VDDA when unused."+ },+ {+ "number": "54",+ "name": "VDDA",+ "type": "power_in",+ "description": "3.3V analog supply; place a minimum 2.2µF decoupling capacitor connected to VSSA on each VDDA pin."+ },+ {+ "number": "55",+ "name": "VREFHID",+ "type": "input",+ "description": "ADC-D high reference voltage; must be driven by an external circuit, requires at least 2.2µF (12-bit mode) or 22µF (16-bit mode) between VREFHID and VREFLOD, and must not be externally loaded; tie to VDDA when unused."+ },+ {+ "number": "56",+ "name": "ADCIND0/CMPIN7P",+ "type": "input",+ "description": "ADC-D input 0 (also comparator 7 positive input CMPIN7P)."+ },+ {+ "number": "57",+ "name": "ADCIND1/CMPIN7N",+ "type": "input",+ "description": "ADC-D input 1 (also comparator 7 negative input CMPIN7N)."+ },+ {+ "number": "58",+ "name": "ADCIND2/CMPIN8P",+ "type": "input",+ "description": "ADC-D input 2 (also comparator 8 positive input CMPIN8P)."+ },+ {+ "number": "59",+ "name": "ADCIND3/CMPIN8N",+ "type": "input",+ "description": "ADC-D input 3 (also comparator 8 negative input CMPIN8N)."+ },+ {+ "number": "60",+ "name": "ADCIND4",+ "type": "input",+ "description": "ADC-D input 4."+ },+ {+ "number": "61",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "62",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "63",+ "name": "GPIO30",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO30 with peripheral mux options (CANA_RX, EMIF1_CLK, MCAN_RX, EQEP3_STROBE, EPWM16A and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "64",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO28 with peripheral mux options (SCIA_RX, EMIF1_CS4n, OUTPUTXBAR5, EQEP3_A, SD2_D3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "65",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO29 with peripheral mux options (SCIA_TX, EMIF1_SDCKE, OUTPUTXBAR6, EQEP3_B, ESC_SYNC0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "66",+ "name": "GPIO31",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO31 with peripheral mux options (CANA_TX, EMIF1_WEn, MCAN_TX, OUTPUTXBAR8, EQEP3_INDEX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "67",+ "name": "GPIO32",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO32 with peripheral mux options (I2CA_SDA, EMIF1_CS0n, SPIA_SIMO, CLB_OUTPUTXBAR1, EMIF1_OEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "68",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "69",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO33 with peripheral mux options (I2CA_SCL, EMIF1_RNW, SPIA_SOMI, CLB_OUTPUTXBAR2, EMIF1_BA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "70",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO34 with peripheral mux options (OUTPUTXBAR1, EMIF1_CS2n, SPIA_CLK, I2CB_SDA, ENET_MII_CRS and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "71",+ "name": "GPIO35",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO35 with peripheral mux options (SCIA_RX, EMIF1_CS3n, SPIA_STEn, I2CB_SCL, ENET_MII_COL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "72",+ "name": "VDD3VFL",+ "type": "power_in",+ "description": "3.3V flash supply pin; place a minimum 0.1µF decoupling capacitor on each VDD3VFL pin."+ },+ {+ "number": "73",+ "name": "FLT1",+ "type": "bidirectional",+ "description": "Flash test pin 1, reserved for TI; must be left unconnected."+ },+ {+ "number": "74",+ "name": "FLT2",+ "type": "bidirectional",+ "description": "Flash test pin 2, reserved for TI; must be left unconnected."+ },+ {+ "number": "75",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "76",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "77",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input with internal pull-up; data is clocked into the selected register on the rising edge of TCK."+ },+ {+ "number": "78",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output; contents of the selected register are shifted out on the falling edge of TCK."+ },+ {+ "number": "79",+ "name": "TRSTn",+ "type": "input",+ "description": "JTAG test reset with internal pull-down and ~50ns glitch filter; must be held low in normal operation, and an external pull-down of 2.2kΩ to 10kΩ is typically used."+ },+ {+ "number": "80",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select with internal pull-up; an external 2.2kΩ pull-up to VDDIO is recommended on the board."+ },+ {+ "number": "81",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock with internal pull-up."+ },+ {+ "number": "82",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "83",+ "name": "GPIO36",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO36 with peripheral mux options (SCIA_TX, EMIF1_WAIT, CANA_RX, CLB_OUTPUTXBAR5, EMIF1_A1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "84",+ "name": "GPIO37",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO37 with peripheral mux options (OUTPUTXBAR2, EMIF1_OEn, CANA_TX, CLB_OUTPUTXBAR6, EMIF1_A2 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "85",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO38 with peripheral mux options (EMIF1_A0, SCIC_TX, CANB_TX, CLB_OUTPUTXBAR7, EMIF1_A3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "86",+ "name": "GPIO39",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO39 with peripheral mux options (EMIF1_A1, SCIC_RX, CANB_RX, CLB_OUTPUTXBAR8, EMIF1_A4 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "87",+ "name": "GPIO40",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO40 with peripheral mux options (EMIF1_A2, I2CB_SDA, ENET_MII_CRS, ESC_I2C_SDA and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "88",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "89",+ "name": "GPIO41",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO41 with peripheral mux options (EMIF1_A3, I2CB_SCL, ENET_REVMII_MDIO_RST, ENET_MII_COL, ESC_I2C_SCL and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "90",+ "name": "GPIO48",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO48 with peripheral mux options (OUTPUTXBAR3, EMIF1_A8, SCIA_TX, SD1_D1, ENET_PPS1 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "91",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "92",+ "name": "ERRORSTS",+ "type": "output",+ "description": "Error status output; requires an external pull-down resistor when used."+ },+ {+ "number": "93",+ "name": "GPIO49",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO49 with peripheral mux options (OUTPUTXBAR4, EMIF1_A9, SCIA_RX, SD1_C1, ENET_MII_RX_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "94",+ "name": "GPIO50",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO50 with peripheral mux options (EQEP1_A, EMIF1_A10, SPIC_SIMO, SD1_D2, ENET_MII_RX_DV and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "95",+ "name": "GPIO51",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO51 with peripheral mux options (EQEP1_B, EMIF1_A11, SPIC_SOMI, SD1_C2, ENET_MII_RX_ERR and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "96",+ "name": "GPIO52",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO52 with peripheral mux options (EQEP1_STROBE, EMIF1_A12, SPIC_CLK, SD1_D3, ENET_MII_RX_DATA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "97",+ "name": "GPIO53",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO53 with peripheral mux options (EQEP1_INDEX, EMIF1_D31, EMIF2_D15, SPIC_STEn, SD1_C3 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "98",+ "name": "GPIO54",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO54 with peripheral mux options (SPIA_SIMO, EMIF1_D30, EMIF2_D14, EQEP2_A, SCIB_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "99",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "100",+ "name": "GPIO55",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO55 with peripheral mux options (SPIA_SOMI, EMIF1_D29, EMIF2_D13, EQEP2_B, SCIB_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "101",+ "name": "GPIO56",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO56 with peripheral mux options (SPIA_CLK, EMIF1_D28, EMIF2_D12, EQEP2_STROBE, SCIC_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "102",+ "name": "GPIO57",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO57 with peripheral mux options (SPIA_STEn, EMIF1_D27, EMIF2_D11, EQEP2_INDEX, SCIC_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "103",+ "name": "GPIO58",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO58 with peripheral mux options (MCLKRA, EMIF1_D26, EMIF2_D10, OUTPUTXBAR1, SPIB_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "104",+ "name": "GPIO59",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO59 with peripheral mux options (MFSRA, EMIF1_D25, EMIF2_D9, OUTPUTXBAR2, SPIB_STEn and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "105",+ "name": "GPIO60",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO60 with peripheral mux options (MCLKRB, EMIF1_D24, EMIF2_D8, OUTPUTXBAR3, SPIB_SIMO and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "106",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "107",+ "name": "GPIO61",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO61 with peripheral mux options (MFSRB, EMIF1_D23, EMIF2_D7, OUTPUTXBAR4, SPIB_SOMI and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "108",+ "name": "GPIO62",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO62 with peripheral mux options (SCIC_RX, EMIF1_D22, EMIF2_D6, EQEP3_A, CANA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "109",+ "name": "GPIO63",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO63 with peripheral mux options (SCIC_TX, EMIF1_D21, EMIF2_D5, EQEP3_B, CANA_TX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "110",+ "name": "GPIO64",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO64 with peripheral mux options (EMIF1_D20, EMIF2_D4, EQEP3_STROBE, SCIA_RX, SSIA_RX and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "111",+ "name": "GPIO65",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO65 with peripheral mux options (EMIF1_D19, EMIF2_D3, EQEP3_INDEX, SCIA_TX, SSIA_CLK and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "112",+ "name": "GPIO66",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO66 with peripheral mux options (EMIF1_D18, EMIF2_D2, I2CB_SDA, SSIA_FSS, ENET_MII_RX_DATA0 and others per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "113",+ "name": "GPIO44",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO44 with peripheral mux options (EMIF1_A4, ENET_MII_TX_CLK, ESC_TX1_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "114",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "115",+ "name": "GPIO45",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO45 with peripheral mux options (EMIF1_A5, ENET_MII_TX_EN, ESC_TX1_ENA per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "116",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "117",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "118",+ "name": "GPIO133/AUXCLKIN",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO133; alternate function AUXCLKIN is the single-ended 3.3V auxiliary clock input for the auxiliary PLL and CPU Timer 2."+ },+ {+ "number": "119",+ "name": "NC2",+ "type": "unconnected",+ "description": "No internal connection; may be left open or tied to VSS or VDDIO, and tying to VDDIO (3.3V) is recommended for PCB compatibility with other C2000 devices."+ },+ {+ "number": "120",+ "name": "VDDOSC",+ "type": "power_in",+ "description": "3.3V supply for the on-chip crystal oscillator (X1/X2) and the two internal zero-pin oscillators; place a minimum 0.1µF decoupling capacitor on each pin."+ },+ {+ "number": "121",+ "name": "X2",+ "type": "output",+ "description": "Crystal oscillator output; connect a quartz crystal circuit between X1 and X2 when using the crystal mode."+ },+ {+ "number": "122",+ "name": "VSSOSC",+ "type": "power_in",+ "description": "Crystal oscillator ground; when an external crystal is used, connect to the crystal oscillator circuit ground reference rather than the board ground, otherwise it may be tied to board ground."+ },+ {+ "number": "123",+ "name": "X1",+ "type": "input",+ "description": "Crystal oscillator or single-ended clock input; initialization software must configure this pin before enabling the crystal oscillator, and it can accept a single-ended 3.3V-level clock."+ },+ {+ "number": "124",+ "name": "XRSn",+ "type": "bidirectional",+ "description": "Open-drain device reset input and watchdog reset output with internal pull-up; a 2.2kΩ to 10kΩ resistor to VDDIO is required, and any noise filter capacitor to VSS must be 100nF or less."+ },+ {+ "number": "125",+ "name": "VDDOSC",+ "type": "power_in",+ "description": "3.3V supply for the on-chip crystal oscillator (X1/X2) and the two internal zero-pin oscillators; place a minimum 0.1µF decoupling capacitor on each pin."+ },+ {+ "number": "126",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "127",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "128",+ "name": "GPIO46",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO46 with peripheral mux options (EMIF1_A6, SCID_RX, ENET_MII_TX_ERR, ESC_MDIO_CLK per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "129",+ "name": "GPIO47",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO47 with peripheral mux options (EMIF1_A7, SCID_TX, ENET_PPS0, ESC_MDIO_DATA per the GPIO mux table); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "130",+ "name": "GPIO42",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO42 with peripheral mux options (I2CA_SDA, ENET_MDIO_CLK, UARTA_TX, SCIA_TX); alternate function USB0DM (USB-0 PHY differential data) when GPBAMSEL[10]=1."+ },+ {+ "number": "131",+ "name": "GPIO43",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO43 with peripheral mux options (I2CA_SCL, ENET_MDIO_DATA, UARTA_RX, SCIA_RX); alternate function USB0DP (USB-0 PHY differential data) when GPBAMSEL[11]=1."+ },+ {+ "number": "132",+ "name": "GPIO67",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO67 with peripheral mux options (EMIF1_D17, EMIF2_D1, ENET_MII_RX_CLK, ENET_REVMII_MDIO_RST, SD1_D3); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "133",+ "name": "GPIO68",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO68 with peripheral mux options (EMIF1_D16, EMIF2_D0, ENET_MII_INTR, SD1_C3, ESC_PHY1_LINKSTATUS); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "134",+ "name": "GPIO69",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO69 with peripheral mux options (EMIF1_D15, I2CB_SCL, ENET_MII_TX_EN, ENET_MII_RX_CLK, SD1_D4, SPIC_SIMO); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "135",+ "name": "GPIO70",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO70 with peripheral mux options (EMIF1_D14, CANA_RX, SCIB_TX, MCAN_RX, ENET_MII_RX_DV, SPIC_SOMI); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "136",+ "name": "GPIO71",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO71 with peripheral mux options (EMIF1_D13, CANA_TX, SCIB_RX, MCAN_TX, ENET_MII_RX_DATA0, SPIC_CLK); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "137",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "138",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "139",+ "name": "GPIO72",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO72 with peripheral mux options (EMIF1_D12, CANB_TX, SCIC_TX, ENET_MII_RX_DATA1, ENET_MII_TX_DATA3, SPIC_STEn); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "140",+ "name": "GPIO73",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO73 with peripheral mux options (EMIF1_D11, XCLKOUT, CANB_RX, SCIC_RX, ENET_RMII_CLK, SD2_D2); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "141",+ "name": "GPIO74",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO74 with peripheral mux options (EMIF1_D10, MCAN_TX, ENET_MII_TX_DATA1, SD2_C2, ESC_TX1_DATA1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "142",+ "name": "GPIO75",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO75 with peripheral mux options (EMIF1_D9, MCAN_RX, ENET_MII_TX_DATA0, SD2_D3, ESC_TX1_DATA0); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "143",+ "name": "GPIO76",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO76 with peripheral mux options (EMIF1_D8, SCID_TX, ENET_MII_RX_ERR, SD2_C3, ESC_PHY_RESETn); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "144",+ "name": "GPIO77",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO77 with peripheral mux options (EMIF1_D7, SCID_RX, SD2_D4, ESC_RX0_CLK); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "145",+ "name": "GPIO78",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO78 with peripheral mux options (EMIF1_D6, EQEP2_A, SD2_C4, ESC_RX0_DV); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "146",+ "name": "GPIO79",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO79 with peripheral mux options (EMIF1_D5, EQEP2_B, SD2_D1, ESC_RX0_ERR); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "147",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "148",+ "name": "GPIO80",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO80 with peripheral mux options (EMIF1_D4, EQEP2_STROBE, SD2_C1, ESC_RX0_DATA0); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "149",+ "name": "GPIO81",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO81 with peripheral mux options (EMIF1_D3, EQEP2_INDEX, ESC_RX0_DATA1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "150",+ "name": "GPIO82",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO82 with peripheral mux options (EMIF1_D2, ESC_RX0_DATA2); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "151",+ "name": "GPIO83",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO83 with peripheral mux options (EMIF1_D1, ESC_RX0_DATA3); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "152",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "153",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "154",+ "name": "GPIO84",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO84 with peripheral mux options (SCIA_TX, MDXB, UARTA_TX, ESC_TX0_ENA, MDXA); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "155",+ "name": "GPIO85",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO85 with peripheral mux options (EMIF1_D0, SCIA_RX, MDRB, UARTA_RX, ESC_TX0_CLK, MDRA); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "156",+ "name": "GPIO86",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO86 with peripheral mux options (EMIF1_A13, EMIF1_CAS, SCIB_TX, MCLKXB, ESC_PHY0_LINKSTATUS, MCLKXA); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "157",+ "name": "GPIO87",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO87 with peripheral mux options (EMIF1_A14, EMIF1_RAS, SCIB_RX, MFSXB, EMIF1_DQM3, ESC_TX0_DATA0, MFSXA); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "158",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "159",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "160",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO0 with peripheral mux options (EPWM1A, I2CA_SDA, CM-I2CA_SDA, ESC_GPI0, FSITXA_D0); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "161",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO1 with peripheral mux options (EPWM1B, MFSRB, I2CA_SCL, CM-I2CA_SCL, ESC_GPI1, FSITXA_D1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "162",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO2 with peripheral mux options (EPWM2A, OUTPUTXBAR1, I2CB_SDA, ESC_GPI2, FSITXA_CLK); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "163",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO3 with peripheral mux options (EPWM2B, OUTPUTXBAR2, MCLKRB, I2CB_SCL, ESC_GPI3, FSIRXA_D0); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "164",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO4 with peripheral mux options (EPWM3A, OUTPUTXBAR3, CANA_TX, MCAN_TX, ESC_GPI4, FSIRXA_D1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "165",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO5 with peripheral mux options (EPWM3B, MFSRA, OUTPUTXBAR3, CANA_RX, MCAN_RX, ESC_GPI5, FSIRXA_CLK); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "166",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO6 with peripheral mux options (EPWM4A, OUTPUTXBAR4, EXTSYNCOUT, EQEP3_A, CANB_TX, ESC_GPI6, FSITXB_D0); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "167",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO7 with peripheral mux options (EPWM4B, MCLKRA, OUTPUTXBAR5, EQEP3_B, CANB_RX, ESC_GPI7, FSITXB_D1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "168",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3V digital I/O supply; place a minimum 0.1µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "169",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2V digital logic supply; place about 20µF minimum total decoupling near the VDD pins and a 56Ω (±10%) resistor between VDD and VSS."+ },+ {+ "number": "170",+ "name": "GPIO88",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO88 with peripheral mux options (EMIF1_A15, EMIF1_DQM0, EMIF1_DQM1, ESC_TX0_DATA1); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "171",+ "name": "GPIO89",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO89 with peripheral mux options (EMIF1_A16, EMIF1_DQM1, SCIC_TX, EMIF1_CAS, ESC_TX0_DATA2); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "172",+ "name": "GPIO90",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO90 with peripheral mux options (EMIF1_A17, EMIF1_DQM2, SCIC_RX, EMIF1_RAS, ESC_TX0_DATA3); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "173",+ "name": "GPIO91",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO91 with peripheral mux options (EMIF1_A18, EMIF1_DQM3, I2CA_SDA, EMIF1_DQM2, PMBUSA_SCL, SSIA_TX, FSIRXF_D0, CLB_OUTPUTXBAR1, SPID_SIMO); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "174",+ "name": "GPIO92",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO92 with peripheral mux options (EMIF1_A19, EMIF1_BA1, I2CA_SCL, EMIF1_DQM0, PMBUSA_SDA, SSIA_RX, FSIRXF_D1, CLB_OUTPUTXBAR2, SPID_SOMI); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "175",+ "name": "GPIO93",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO93 with peripheral mux options (EMIF1_BA0, SCID_TX, PMBUSA_ALERT, SSIA_CLK, FSIRXF_CLK, CLB_OUTPUTXBAR3, SPID_CLK); internal pull-up is disabled by default and software-enabled."+ },+ {+ "number": "176",+ "name": "GPIO94",+ "type": "bidirectional",+ "description": "General-purpose I/O GPIO94 with peripheral mux options (SCID_RX, EMIF1_BA1, PMBUSA_CTL, SSIA_FSS, FSIRXG_D0, CLB_OUTPUTXBAR4, SPID_STEn); internal pull-up is disabled by default and software-enabled."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The 176-pin PTP package has no individually numbered VSS pins; ground is provided only through the P; Pin-to-signal map (pins 1-176) was taken from the 176-pin top-view figure 6-6 and cross-checked agai; Dual-function analog pins are listed under their ADC name with the comparator or DAC alternate in th",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 139,+ "cost_usd": 1.2251,+ "at": "2026-10-08T18:08:54"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28384d-q1",+ "pages": 359,+ "sha256": "b16044f781d66c38",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 176,+ "described": 176,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "f28386dptps.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 26,+ 26,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "af405b3ced8ef09a67c3c4732e526f53f88a9b9f83ce7d10b8fa299331f6842a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "f28386dptps-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 26,+ 26,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4a3b0518cd498797bd985f80b03bb2eb9f4e0aec600cd45d68b71983eed5763c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}