component
F280049CPMSR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+101@@ -0,0 +1,101 @@+# F280049CPMSR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++F280049CPMSR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO29 | bidirectional | General-purpose I/O 29 with selectable alternates SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS (active-low error status output). |+| 2 | GPIO28 | bidirectional | General-purpose I/O 28 with selectable alternates SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, SD1_D3, EQEP2_STROBE, LINA_TX, SPIB_CLK and ERRORSTS (active-low error status output). |+| 3 | XRSn | bidirectional | Device reset input and watchdog reset output, an open-drain pin with internal pull-up; a 2.2 kΩ to 10 kΩ resistor should be placed between XRSn and VDDIO, and any noise-filter capacitor to VSS should be 100 nF or less. |+| 4 | VDD | power_in | 1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins. |+| 5 | VSS | power_in | Digital ground pin that must be connected to the board ground. |+| 6 | A6/PGA5_OF | passive | ADC-A analog input 6, also PGA-5 output filter (optional) and CMPSS-5 input, with digital input AIO228. |+| 7 | B2/C6/PGA3_OF | passive | ADC-B input 2 and ADC-C input 6, also PGA-3 output filter (optional) and CMPSS-3 input. |+| 8 | B3/VDAC | passive | ADC-B input 3 and optional external reference for the on-chip DAC; a 100 pF capacitor to VSSA is always present and at least one 1 µF capacitor is required if used as DAC reference. |+| 9 | A2/B6/PGA1_OF | passive | ADC-A input 2 and ADC-B input 6, also PGA-1 output filter (optional) and CMPSS-1 input. |+| 10 | PGA1_GND/PGA3_GND/PGA5_GND | power_in | Kelvin ground reference for the PGA-1, PGA-3 and PGA-5 inputs, ideally equal to VSSA. |+| 11 | C4/PGA5_IN | passive | ADC-C input 4 and PGA-5 input. |+| 12 | C0/PGA1_IN | passive | ADC-C input 0 and PGA-1 input. |+| 13 | C2/PGA3_IN | passive | ADC-C input 2 and PGA-3 input. |+| 14 | A1/DACB_OUT | passive | ADC-A input 1 and buffered DAC-B output. |+| 15 | A0/B15/C15/DACA_OUT | passive | ADC-A input 0, ADC-B input 15 and ADC-C input 15, also buffered DAC-A output. |+| 16 | VREFHIA/VREFHIB/VREFHIC | bidirectional | ADC-A/B/C high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between each VREFHIx and its VREFLOx pin and no external loading. |+| 17 | VREFLOA/VREFLOB/VREFLOC | passive | ADC-A, ADC-B and ADC-C low reference voltage pins. |+| 18 | C1/PGA2_IN | passive | ADC-C input 1 and PGA-2 input. |+| 19 | C3/PGA4_IN | passive | ADC-C input 3 and PGA-4 input. |+| 20 | PGA2_GND/PGA4_GND/PGA6_GND | power_in | Kelvin ground reference for the PGA-2, PGA-4 and PGA-6 inputs, ideally equal to VSSA. |+| 21 | VSSA | power_in | Analog ground pin. |+| 22 | VDDA | power_in | 3.3 V analog supply pin; a decoupling capacitor of at least 2.2 µF connected to VSSA should be placed on each VDDA pin. |+| 23 | A4/B8/PGA2_OF | passive | ADC-A input 4 and ADC-B input 8, also PGA-2 output filter (optional) and CMPSS-2 input. |+| 24 | B4/C8/PGA4_OF | passive | ADC-B input 4 and ADC-C input 8, also PGA-4 output filter (optional) and CMPSS-4 input. |+| 25 | A10/B1/C10/PGA7_OF | passive | ADC-A input 10, ADC-B input 1 and ADC-C input 10, also PGA-7 output filter (optional) and CMPSS-7 input. |+| 26 | VSS | power_in | Digital ground pin that must be connected to the board ground. |+| 27 | VDD | power_in | 1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins. |+| 28 | VDDIO | power_in | 3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin. |+| 29 | GPIO13 | bidirectional | General-purpose I/O 13 with selectable alternates EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK. |+| 30 | GPIO12 | bidirectional | General-purpose I/O 12 with selectable alternates EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0. |+| 31 | GPIO11 | bidirectional | General-purpose I/O 11 with selectable alternates EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1. |+| 32 | GPIO33 | bidirectional | General-purpose I/O 33 with selectable alternates I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX. |+| 33 | GPIO16 | bidirectional | General-purpose I/O 16 with selectable alternates SPIA_SIMO, CANB_TX, OUTPUTXBAR7, EPWM5_A, SCIA_TX, SD1_D1, EQEP1_STROBE, PMBUSA_SCL and XCLKOUT. |+| 34 | GPIO17 | bidirectional | General-purpose I/O 17 with selectable alternates SPIA_SOMI, CANB_RX, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1, EQEP1_INDEX and PMBUSA_SDA. |+| 35 | GPIO24 | bidirectional | General-purpose I/O 24 with selectable alternates OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, PMBUSA_SCL, SCIA_TX and ERRORSTS (active-low error status output). |+| 36 | TCK | input | JTAG test clock input with internal pull-up. |+| 37 | GPIO37/TDO | bidirectional | JTAG test data output (TDO) by default, tri-stated when no JTAG activity; alternates include OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B and PMBUSA_ALERT, and an internal pull-up or external pull-up should be used to avoid a floating input. |+| 38 | TMS | bidirectional | JTAG test mode select with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended on the board. |+| 39 | GPIO35/TDI | bidirectional | JTAG test data input (TDI) by default with internal pull-up disabled; if used as TDI an internal pull-up should be enabled or an external pull-up added, and alternates include SCIA_RX, I2CA_SDA, CANA_RX, PMBUSA_SCL, LINA_RX and EQEP1_A. |+| 40 | GPIO32 | bidirectional | General-purpose I/O 32 with selectable alternates I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX. |+| 41 | GPIO18_X2 | bidirectional | General-purpose I/O 18 or crystal oscillator output X2; GPIO18 and its mux options are usable only when INTOSC clocks the system and X1 has an external pull-down (1 kΩ recommended). |+| 42 | X1 | bidirectional | Crystal oscillator input or single-ended 3.3 V clock input; device software must configure this pin before enabling the crystal oscillator. |+| 43 | VDDIO | power_in | 3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin. |+| 44 | VDD | power_in | 1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins. |+| 45 | VSS | power_in | Digital ground pin that must be connected to the board ground. |+| 46 | VREGENZ | input | Internal regulator enable with internal pull-down; tie directly to VSS to enable the internal VREG and to VDDIO to use an external 1.2 V supply. |+| 47 | GPIO8 | bidirectional | General-purpose I/O 8 with selectable alternates EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1. |+| 48 | GPIO4 | bidirectional | General-purpose I/O 4 with selectable alternates EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK. |+| 49 | GPIO3 | bidirectional | General-purpose I/O 3 with selectable alternates EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0. |+| 50 | GPIO2 | bidirectional | General-purpose I/O 2 with selectable alternates EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1. |+| 51 | GPIO1 | bidirectional | General-purpose I/O 1 with selectable alternates EPWM1_B and I2CA_SCL (open-drain). |+| 52 | GPIO0 | bidirectional | General-purpose I/O 0 with selectable alternates EPWM1_A and I2CA_SDA (open-drain). |+| 53 | VDDIO_SW | power_in | 3.3 V supply for the internal DC/DC regulator; must be connected to the same supply as VDDIO and needs a 20 µF bulk input capacitor when the DC/DC is used. |+| 54 | GPIO23_VSW | bidirectional | General-purpose I/O 23, which is the internal DC/DC switch output (VSW) when DCDCEN = 1; TI recommends an alternate GPIO or use only where fast switching response is not needed. |+| 55 | VSS_SW | power_in | Internal DC/DC regulator ground that must be connected to VSS. |+| 56 | GPIO22_VFBSW | bidirectional | General-purpose I/O 22, which is the internal DC/DC feedback signal (VFBSW) by default; when the DC/DC is used this pin must connect to the node where L(VSW) connects to the VDD rail, as close to the device as possible. |+| 57 | GPIO7 | bidirectional | General-purpose I/O 7 with selectable alternates EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK. |+| 58 | VSS | power_in | Digital ground pin that must be connected to the board ground. |+| 59 | VDD | power_in | 1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins. |+| 60 | VDDIO | power_in | 3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin. |+| 61 | GPIO5 | bidirectional | General-purpose I/O 5 with selectable alternates EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1. |+| 62 | GPIO9 | bidirectional | General-purpose I/O 9 with selectable alternates EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0. |+| 63 | GPIO10 | bidirectional | General-purpose I/O 10 with selectable alternates EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK. |+| 64 | GPIO6 | bidirectional | General-purpose I/O 6 with selectable alternates EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-64(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `F280049CPMSR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `f280049cpmsr-etched.step` / `f280049cpmsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `f280049cpmsr.step` / `f280049cpmsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f280045) (277 pp, sha256 `867e7bb5ada6819c`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/f280049cpmsr-datasheet.pdf)
page.jsonadded+536@@ -0,0 +1,536 @@+{+ "slug": "f280049cpmsr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "f280049cpmsr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "f280049cpmsr.kicad_sym",+ "f280049cpmsr.kicad_mod",+ "f280049cpmsr.glb",+ "f280049cpmsr.step",+ "f280049cpmsr.lbr",+ "docs/hero.png",+ "docs/f280049cpmsr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "f280049cpmsr-hero.glb",+ "f280049cpmsr-hero.overlay.json"+ ],+ "component": {+ "mpn": "F280049CPMSR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f280045",+ "parts": {+ "symbol": "f280049cpmsr.kicad_sym",+ "footprint": "f280049cpmsr.kicad_mod",+ "model_3d": "f280049cpmsr-hero.glb",+ "model_3d_plain": "f280049cpmsr.glb",+ "model_3d_step": "f280049cpmsr-etched.step",+ "model_3d_step_plain": "f280049cpmsr.step",+ "lbr": "f280049cpmsr.lbr"+ },+ "distributor_links": {+ "lcsc": "C5218686",+ "digikey": "296-F280049CPMSRTR-ND",+ "mouser": "595-F280049CPMSR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:01:33Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-F280049CPMSRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-F280049CPMSR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 with selectable alternates SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS (active-low error status output)."+ },+ {+ "number": "2",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 with selectable alternates SCIA_RX, EPWM7_A, OUTPUTXBAR5, EQEP1_A, SD1_D3, EQEP2_STROBE, LINA_TX, SPIB_CLK and ERRORSTS (active-low error status output)."+ },+ {+ "number": "3",+ "name": "XRSn",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output, an open-drain pin with internal pull-up; a 2.2 kΩ to 10 kΩ resistor should be placed between XRSn and VDDIO, and any noise-filter capacitor to VSS should be 100 nF or less."+ },+ {+ "number": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin that must be connected to the board ground."+ },+ {+ "number": "6",+ "name": "A6/PGA5_OF",+ "type": "passive",+ "description": "ADC-A analog input 6, also PGA-5 output filter (optional) and CMPSS-5 input, with digital input AIO228."+ },+ {+ "number": "7",+ "name": "B2/C6/PGA3_OF",+ "type": "passive",+ "description": "ADC-B input 2 and ADC-C input 6, also PGA-3 output filter (optional) and CMPSS-3 input."+ },+ {+ "number": "8",+ "name": "B3/VDAC",+ "type": "passive",+ "description": "ADC-B input 3 and optional external reference for the on-chip DAC; a 100 pF capacitor to VSSA is always present and at least one 1 µF capacitor is required if used as DAC reference."+ },+ {+ "number": "9",+ "name": "A2/B6/PGA1_OF",+ "type": "passive",+ "description": "ADC-A input 2 and ADC-B input 6, also PGA-1 output filter (optional) and CMPSS-1 input."+ },+ {+ "number": "10",+ "name": "PGA1_GND/PGA3_GND/PGA5_GND",+ "type": "power_in",+ "description": "Kelvin ground reference for the PGA-1, PGA-3 and PGA-5 inputs, ideally equal to VSSA."+ },+ {+ "number": "11",+ "name": "C4/PGA5_IN",+ "type": "passive",+ "description": "ADC-C input 4 and PGA-5 input."+ },+ {+ "number": "12",+ "name": "C0/PGA1_IN",+ "type": "passive",+ "description": "ADC-C input 0 and PGA-1 input."+ },+ {+ "number": "13",+ "name": "C2/PGA3_IN",+ "type": "passive",+ "description": "ADC-C input 2 and PGA-3 input."+ },+ {+ "number": "14",+ "name": "A1/DACB_OUT",+ "type": "passive",+ "description": "ADC-A input 1 and buffered DAC-B output."+ },+ {+ "number": "15",+ "name": "A0/B15/C15/DACA_OUT",+ "type": "passive",+ "description": "ADC-A input 0, ADC-B input 15 and ADC-C input 15, also buffered DAC-A output."+ },+ {+ "number": "16",+ "name": "VREFHIA/VREFHIB/VREFHIC",+ "type": "bidirectional",+ "description": "ADC-A/B/C high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between each VREFHIx and its VREFLOx pin and no external loading."+ },+ {+ "number": "17",+ "name": "VREFLOA/VREFLOB/VREFLOC",+ "type": "passive",+ "description": "ADC-A, ADC-B and ADC-C low reference voltage pins."+ },+ {+ "number": "18",+ "name": "C1/PGA2_IN",+ "type": "passive",+ "description": "ADC-C input 1 and PGA-2 input."+ },+ {+ "number": "19",+ "name": "C3/PGA4_IN",+ "type": "passive",+ "description": "ADC-C input 3 and PGA-4 input."+ },+ {+ "number": "20",+ "name": "PGA2_GND/PGA4_GND/PGA6_GND",+ "type": "power_in",+ "description": "Kelvin ground reference for the PGA-2, PGA-4 and PGA-6 inputs, ideally equal to VSSA."+ },+ {+ "number": "21",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "22",+ "name": "VDDA",+ "type": "power_in",+ "description": "3.3 V analog supply pin; a decoupling capacitor of at least 2.2 µF connected to VSSA should be placed on each VDDA pin."+ },+ {+ "number": "23",+ "name": "A4/B8/PGA2_OF",+ "type": "passive",+ "description": "ADC-A input 4 and ADC-B input 8, also PGA-2 output filter (optional) and CMPSS-2 input."+ },+ {+ "number": "24",+ "name": "B4/C8/PGA4_OF",+ "type": "passive",+ "description": "ADC-B input 4 and ADC-C input 8, also PGA-4 output filter (optional) and CMPSS-4 input."+ },+ {+ "number": "25",+ "name": "A10/B1/C10/PGA7_OF",+ "type": "passive",+ "description": "ADC-A input 10, ADC-B input 1 and ADC-C input 10, also PGA-7 output filter (optional) and CMPSS-7 input."+ },+ {+ "number": "26",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin that must be connected to the board ground."+ },+ {+ "number": "27",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins."+ },+ {+ "number": "28",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin."+ },+ {+ "number": "29",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O 13 with selectable alternates EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK."+ },+ {+ "number": "30",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with selectable alternates EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0."+ },+ {+ "number": "31",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O 11 with selectable alternates EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1."+ },+ {+ "number": "32",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with selectable alternates I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX."+ },+ {+ "number": "33",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 with selectable alternates SPIA_SIMO, CANB_TX, OUTPUTXBAR7, EPWM5_A, SCIA_TX, SD1_D1, EQEP1_STROBE, PMBUSA_SCL and XCLKOUT."+ },+ {+ "number": "34",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 with selectable alternates SPIA_SOMI, CANB_RX, OUTPUTXBAR8, EPWM5_B, SCIA_RX, SD1_C1, EQEP1_INDEX and PMBUSA_SDA."+ },+ {+ "number": "35",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose I/O 24 with selectable alternates OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, PMBUSA_SCL, SCIA_TX and ERRORSTS (active-low error status output)."+ },+ {+ "number": "36",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input with internal pull-up."+ },+ {+ "number": "37",+ "name": "GPIO37/TDO",+ "type": "bidirectional",+ "description": "JTAG test data output (TDO) by default, tri-stated when no JTAG activity; alternates include OUTPUTXBAR2, I2CA_SCL, SCIA_TX, CANA_TX, LINA_TX, EQEP1_B and PMBUSA_ALERT, and an internal pull-up or external pull-up should be used to avoid a floating input."+ },+ {+ "number": "38",+ "name": "TMS",+ "type": "bidirectional",+ "description": "JTAG test mode select with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended on the board."+ },+ {+ "number": "39",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "JTAG test data input (TDI) by default with internal pull-up disabled; if used as TDI an internal pull-up should be enabled or an external pull-up added, and alternates include SCIA_RX, I2CA_SDA, CANA_RX, PMBUSA_SCL, LINA_RX and EQEP1_A."+ },+ {+ "number": "40",+ "name": "GPIO32",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with selectable alternates I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX."+ },+ {+ "number": "41",+ "name": "GPIO18_X2",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 or crystal oscillator output X2; GPIO18 and its mux options are usable only when INTOSC clocks the system and X1 has an external pull-down (1 kΩ recommended)."+ },+ {+ "number": "42",+ "name": "X1",+ "type": "bidirectional",+ "description": "Crystal oscillator input or single-ended 3.3 V clock input; device software must configure this pin before enabling the crystal oscillator."+ },+ {+ "number": "43",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin."+ },+ {+ "number": "44",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins."+ },+ {+ "number": "45",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin that must be connected to the board ground."+ },+ {+ "number": "46",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal regulator enable with internal pull-down; tie directly to VSS to enable the internal VREG and to VDDIO to use an external 1.2 V supply."+ },+ {+ "number": "47",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O 8 with selectable alternates EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1."+ },+ {+ "number": "48",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with selectable alternates EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK."+ },+ {+ "number": "49",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with selectable alternates EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0."+ },+ {+ "number": "50",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with selectable alternates EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1."+ },+ {+ "number": "51",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with selectable alternates EPWM1_B and I2CA_SCL (open-drain)."+ },+ {+ "number": "52",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with selectable alternates EPWM1_A and I2CA_SDA (open-drain)."+ },+ {+ "number": "53",+ "name": "VDDIO_SW",+ "type": "power_in",+ "description": "3.3 V supply for the internal DC/DC regulator; must be connected to the same supply as VDDIO and needs a 20 µF bulk input capacitor when the DC/DC is used."+ },+ {+ "number": "54",+ "name": "GPIO23_VSW",+ "type": "bidirectional",+ "description": "General-purpose I/O 23, which is the internal DC/DC switch output (VSW) when DCDCEN = 1; TI recommends an alternate GPIO or use only where fast switching response is not needed."+ },+ {+ "number": "55",+ "name": "VSS_SW",+ "type": "power_in",+ "description": "Internal DC/DC regulator ground that must be connected to VSS."+ },+ {+ "number": "56",+ "name": "GPIO22_VFBSW",+ "type": "bidirectional",+ "description": "General-purpose I/O 22, which is the internal DC/DC feedback signal (VFBSW) by default; when the DC/DC is used this pin must connect to the node where L(VSW) connects to the VDD rail, as close to the device as possible."+ },+ {+ "number": "57",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with selectable alternates EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK."+ },+ {+ "number": "58",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin that must be connected to the board ground."+ },+ {+ "number": "59",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply pin; TI recommends a minimum total decoupling capacitance of about 20 µF near the VDD pins."+ },+ {+ "number": "60",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply pin; a decoupling capacitor of at least 0.1 µF should be placed on each VDDIO pin."+ },+ {+ "number": "61",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with selectable alternates EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1."+ },+ {+ "number": "62",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O 9 with selectable alternates EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0."+ },+ {+ "number": "63",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O 10 with selectable alternates EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK."+ },+ {+ "number": "64",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with selectable alternates EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package variant: the MPN suffix PM maps to the 64-pin LQFP (10x10). Pin mapping uses the 64 PM Low-P; Cross-check: every pin position in the Figure 5-2 drawing was verified against the 'PM 64' column of; Pin types for multi-function analog pins (ADC inputs that also serve as PGA, CMPSS or DAC outputs) a"+ ],+ "pages_sent": 146,+ "cost_usd": 1.0623,+ "at": "2026-10-07T23:01:06"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f280045",+ "pages": 277,+ "sha256": "867e7bb5ada6819c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "f280049cpmsr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "f280049cpmsr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "27fc9f41c33a60432aaa95ddd0296e1130064c57a394eba53f167fef6255e8bd",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}