component
F280041CPZS
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+137@@ -0,0 +1,137 @@+# F280041CPZS++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)++F280041CPZS from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO28 | bidirectional | General-purpose I/O 28 on the 3.3 V VDDIO domain, with alternate functions including SCIA_RX, EPWM7_A, SD1_D3, SPIB_CLK and ERRORSTS. |+| 2 | XRSn | bidirectional | Device reset input and watchdog reset output (open-drain with internal pull-up); a 2.2 kΩ to 10 kΩ resistor to VDDIO is required, and any noise filter capacitor to VSS must be 100 nF or less. |+| 3 | VDDIO | power_in | 3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin. |+| 4 | VDD | power_in | 1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used. |+| 5 | VSS | power_in | Digital ground; all VSS pins must be connected to board ground. |+| 6 | A6/PGA5_OF | input | ADC-A analog input 6, also the optional PGA-5 output filter pin; analog inputs must stay below VDDA + 0.3 V during operation. |+| 7 | B2/C6/PGA3_OF | input | ADC-B analog input 2 (also ADC-C input 6) and optional PGA-3 output filter pin; analog inputs must stay below VDDA + 0.3 V. |+| 8 | B3/VDAC | input | ADC-B analog input 3 and optional external reference for the on-chip DACs; a 100 pF capacitor to VSSA is always present, and at least 1 µF is required if VDAC is used as DAC reference. |+| 9 | A2/B6/PGA1_OF | input | ADC-A analog input 2 (also ADC-B input 6) and optional PGA-1 output filter pin. |+| 10 | A3 | input | ADC-A analog input 3, also routed to CMPSS-1 comparator inputs. |+| 11 | VDDA | power_in | 3.3 V analog supply; place a minimum 2.2 µF decoupling capacitor to VSSA on each VDDA pin. |+| 12 | VSSA | power_in | Analog ground for the ADC, PGA, DAC and comparator circuits. |+| 13 | PGA5_GND | power_in | PGA-5 Kelvin ground reference; should be bound to VSSA if the PGA is unused. |+| 14 | PGA1_GND | power_in | PGA-1 Kelvin ground reference; should be bound to VSSA if the PGA is unused. |+| 15 | PGA3_GND | power_in | PGA-3 Kelvin ground reference; should be bound to VSSA if the PGA is unused. |+| 16 | PGA5_IN | input | PGA-5 non-inverting input, amplified with programmable gain of 3, 6, 12 or 24. |+| 17 | C4 | input | ADC-C analog input 4, also routed to CMPSS-5 comparator inputs. |+| 18 | PGA1_IN | input | PGA-1 input with programmable gain of 3, 6, 12 or 24. |+| 19 | C0 | input | ADC-C analog input 0, also routed to CMPSS-1 comparator inputs. |+| 20 | PGA3_IN | input | PGA-3 input with programmable gain of 3, 6, 12 or 24. |+| 21 | C2 | input | ADC-C analog input 2, also routed to CMPSS-3 comparator inputs. |+| 22 | A1/DACB_OUT | input | ADC-A analog input 1; alternate function is the buffered 12-bit DAC-B output. |+| 23 | A0/B15/C15/DACA_OUT | input | ADC-A analog input 0 (also ADC-B 15 and ADC-C 15); alternate function is the buffered 12-bit DAC-A output. |+| 24 | VREFHIB/VREFHIC | bidirectional | ADC-B and ADC-C high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between this pin and VREFLO and no external loading. |+| 25 | VREFHIA | bidirectional | ADC-A high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between this pin and VREFLOA and no external loading. |+| 26 | VREFLOB/VREFLOC | input | ADC-B and ADC-C low reference, bound to VSSA in typical use. |+| 27 | VREFLOA | input | ADC-A low reference, bound to VSSA in typical use. |+| 28 | C5/PGA6_IN | input | ADC-C analog input 5; alternate function is the PGA-6 input, and it is also routed to CMPSS-6 comparator inputs. |+| 29 | C1 | input | ADC-C analog input 1, also routed to CMPSS-2 comparator inputs. |+| 30 | PGA2_IN | input | PGA-2 input with programmable gain of 3, 6, 12 or 24. |+| 31 | C3/PGA4_IN | input | ADC-C analog input 3; alternate function is the PGA-4 input, and it is also routed to CMPSS-4 comparator inputs. |+| 32 | PGA2_GND,PGA4_GND,PGA6_GND | power_in | Shared PGA ground references for PGA-2, PGA-4 and PGA-6; bound to VSSA when those PGAs are unused. |+| 33 | VSSA | power_in | Analog ground for the ADC, PGA, DAC and comparator circuits. |+| 34 | VDDA | power_in | 3.3 V analog supply; place a minimum 2.2 µF decoupling capacitor to VSSA on each VDDA pin. |+| 35 | A5 | input | ADC-A analog input 5, also routed to CMPSS-2 comparator inputs. |+| 36 | A4/B8/PGA2_OF | input | ADC-A analog input 4 (also ADC-B input 8) and optional PGA-2 output filter pin. |+| 37 | A8/PGA6_OF | input | ADC-A analog input 8 and optional PGA-6 output filter pin. |+| 38 | A9 | input | ADC-A analog input 9, also routed to CMPSS-6 comparator inputs. |+| 39 | B4/C8/PGA4_OF | input | ADC-B analog input 4 (also ADC-C input 8) and optional PGA-4 output filter pin. |+| 40 | A10/B1/C10/PGA7_OF | input | ADC-A analog input 10 (also ADC-B input 1 and ADC-C input 10) and optional PGA-7 output filter pin. |+| 41 | B0 | input | ADC-B analog input 0, also routed to CMPSS-7 comparator inputs. |+| 42 | PGA7_GND | power_in | PGA-7 Kelvin ground reference; should be bound to VSSA if the PGA is unused. |+| 43 | PGA7_IN | input | PGA-7 input with programmable gain of 3, 6, 12 or 24. |+| 44 | C14 | input | ADC-C analog input 14, also routed to CMPSS-7 comparator inputs. |+| 45 | VSS | power_in | Digital ground; all VSS pins must be connected to board ground. |+| 46 | VDD | power_in | 1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used. |+| 47 | VDDIO | power_in | 3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin. |+| 48 | FLT2 | unconnected | Flash test pin 2, reserved by TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more). |+| 49 | FLT1 | unconnected | Flash test pin 1, reserved by TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more). |+| 50 | GPIO13 | bidirectional | General-purpose I/O 13 with alternate functions including EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK. |+| 51 | GPIO12 | bidirectional | General-purpose I/O 12 with alternate functions including EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0. |+| 52 | GPIO11 | bidirectional | General-purpose I/O 11 with alternate functions including EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1. |+| 53 | GPIO33 | bidirectional | General-purpose I/O 33 with alternate functions including I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX. |+| 54 | GPIO16 | bidirectional | General-purpose I/O 16 with alternate functions including SPIA_SIMO, CANB_TX, EPWM5_A, SCIA_TX, SD1_D1 and XCLKOUT. |+| 55 | GPIO17 | bidirectional | General-purpose I/O 17 with alternate functions including SPIA_SOMI, CANB_RX, EPWM5_B, SCIA_RX, SD1_C1 and PMBUSA_SDA (open-drain). |+| 56 | GPIO24 | bidirectional | General-purpose I/O 24 with alternate functions including OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, SCIA_TX and ERRORSTS (active-low error status output). |+| 57 | GPIO25 | bidirectional | General-purpose I/O 25 with alternate functions including OUTPUTXBAR2, EQEP2_B, SPIB_SOMI, SD1_C1, FSITXA_D1, PMBUSA_SDA (open-drain) and SCIA_RX. |+| 58 | GPIO26 | bidirectional | General-purpose I/O 26 with alternate functions including OUTPUTXBAR3, EQEP2_INDEX, SPIB_CLK, SD1_D2, FSITXA_D0, PMBUSA_CTL and I2CA_SDA (open-drain). |+| 59 | GPIO27 | bidirectional | General-purpose I/O 27 with alternate functions including OUTPUTXBAR4, EQEP2_STROBE, SPIB_STE, SD1_C2, FSITXA_CLK, PMBUSA_ALERT (open-drain) and I2CA_SCL (open-drain). |+| 60 | TCK | input | JTAG test clock input with internal pull-up. |+| 61 | GPIO37/TDO | tri_state | JTAG test data output (default function) that is tri-stated when no JTAG activity is present; an internal or external pull-up is required to avoid a floating input when used as GPIO37. |+| 62 | TMS | bidirectional | JTAG test mode select with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended on the board to hold JTAG in reset during normal operation. |+| 63 | GPIO35/TDI | bidirectional | JTAG test data input (default function); internal pull-up is disabled by default, so an internal pull-up must be enabled or an external pull-up added when used as TDI. |+| 64 | GPIO32 | bidirectional | General-purpose I/O 32 with alternate functions including I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX. |+| 65 | GPIO56 | bidirectional | General-purpose I/O 56 with alternate functions including SPIA_CLK, EQEP2_STROBE, SCIB_TX, SD1_D3, SPIB_SIMO and EQEP1_A. |+| 66 | GPIO57 | bidirectional | General-purpose I/O 57 with alternate functions including SPIA_STE, EQEP2_INDEX, SCIB_RX, SD1_C3, SPIB_SOMI and EQEP1_B. |+| 67 | GPIO58 | bidirectional | General-purpose I/O 58 with alternate functions including OUTPUTXBAR1, SPIB_CLK, SD1_D4, LINA_TX, CANB_TX and EQEP1_STROBE. |+| 68 | GPIO18_X2 | bidirectional | General-purpose I/O 18 or crystal oscillator output X2; GPIO18 is usable only when the system is clocked by INTOSC and X1 has an external pull-down (recommended 1 kΩ). |+| 69 | X1 | bidirectional | Crystal oscillator input or single-ended 3.3 V clock input; device software must configure this pin before enabling the crystal oscillator. |+| 70 | VDDIO | power_in | 3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin. |+| 71 | VDD | power_in | 1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used. |+| 72 | VSS | power_in | Digital ground; all VSS pins must be connected to board ground. |+| 73 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the internal VREG (and DC/DC), or tie to VDDIO to use an external VDD supply. |+| 74 | GPIO8 | bidirectional | General-purpose I/O 8 with alternate functions including EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1. |+| 75 | GPIO4 | bidirectional | General-purpose I/O 4 with alternate functions including EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK. |+| 76 | GPIO3 | bidirectional | General-purpose I/O 3 with alternate functions including EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0. |+| 77 | GPIO2 | bidirectional | General-purpose I/O 2 with alternate functions including EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1. |+| 78 | GPIO1 | bidirectional | General-purpose I/O 1 with alternate functions EPWM1_B and I2CA_SCL (open-drain). |+| 79 | GPIO0 | bidirectional | General-purpose I/O 0 with alternate functions EPWM1_A and I2CA_SDA (open-drain). |+| 80 | VDDIO_SW | power_in | 3.3 V supply for the internal DC/DC regulator; must be connected to VDDIO, with a 20 µF bulk input capacitor when the DC/DC is used. |+| 81 | GPIO23_VSW | bidirectional | General-purpose I/O 23 or DC/DC switch output VSW (when DCDCEN = 1); the pin has about 100 pF internal capacitance, so TI recommends an alternate GPIO for fast-switching use. |+| 82 | VSS_SW | power_in | Internal DC/DC regulator ground; must always be connected to VSS. |+| 83 | GPIO22_VFBSW | bidirectional | General-purpose I/O 22 or DC/DC feedback VFBSW; when the internal DC/DC is used, connect this pin to the node where L(VSW) connects to the VDD rail as close to the device as possible. |+| 84 | GPIO7 | bidirectional | General-purpose I/O 7 with alternate functions including EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK. |+| 85 | GPIO40 | bidirectional | General-purpose I/O 40 with alternate functions including PMBUSA_SDA (open-drain), FSIRXA_D0, SCIB_TX and EQEP1_A. |+| 86 | VSS | power_in | Digital ground; all VSS pins must be connected to board ground. |+| 87 | VDD | power_in | 1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used. |+| 88 | VDDIO | power_in | 3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin. |+| 89 | GPIO5 | bidirectional | General-purpose I/O 5 with alternate functions including EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1. |+| 90 | GPIO9 | bidirectional | General-purpose I/O 9 with alternate functions including EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0. |+| 91 | GPIO39 | bidirectional | General-purpose I/O 39 with alternate functions CANB_RX and FSIRXA_CLK. |+| 92 | GPIO59 | bidirectional | General-purpose I/O 59 with alternate functions including OUTPUTXBAR2, SPIB_STE, SD1_C4, LINA_RX, CANB_RX and EQEP1_INDEX. |+| 93 | GPIO10 | bidirectional | General-purpose I/O 10 with alternate functions including EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK. |+| 94 | GPIO34 | bidirectional | General-purpose I/O 34 with alternate functions OUTPUTXBAR1 and PMBUSA_SDA (open-drain). |+| 95 | GPIO15 | bidirectional | General-purpose I/O 15 with alternate functions including EPWM8_B, SCIB_RX, OUTPUTXBAR4, PMBUSA_SCL (open-drain), SPIB_STE and EQEP2_B. |+| 96 | GPIO14 | bidirectional | General-purpose I/O 14 with alternate functions including EPWM8_A, SCIB_TX, OUTPUTXBAR3, PMBUSA_SDA (open-drain), SPIB_CLK and EQEP2_A. |+| 97 | GPIO6 | bidirectional | General-purpose I/O 6 with alternate functions including EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0. |+| 98 | GPIO30 | bidirectional | General-purpose I/O 30 with alternate functions including CANA_RX, SPIB_SIMO, OUTPUTXBAR7, EQEP1_STROBE and SD1_D4. |+| 99 | GPIO31 | bidirectional | General-purpose I/O 31 with alternate functions including CANA_TX, SPIB_SOMI, OUTPUTXBAR8, EQEP1_INDEX, SD1_C4 and FSIRXA_D1. |+| 100 | GPIO29 | bidirectional | General-purpose I/O 29 with alternate functions including SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-100(14x14) |+| Category | Embedded Processors & Controllers |+| Pins | 100 |++## CAD (KiCad official)++- Symbol: `F280041CPZS`+- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`+- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)+- 3D model files: `f280041cpzs-etched.step` / `f280041cpzs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `f280041cpzs.step` / `f280041cpzs.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f280045) (277 pp, sha256 `867e7bb5ada6819c`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/f280041cpzs-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "f280041cpzs",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "f280041cpzs.kicad_sym",+ "f280041cpzs.kicad_mod",+ "f280041cpzs.glb",+ "f280041cpzs.step",+ "f280041cpzs.lbr",+ "docs/hero.png",+ "docs/f280041cpzs-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "f280041cpzs-hero.glb",+ "f280041cpzs-hero.overlay.json"+ ],+ "component": {+ "mpn": "F280041CPZS",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-100(14x14)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f280045",+ "parts": {+ "symbol": "f280041cpzs.kicad_sym",+ "footprint": "f280041cpzs.kicad_mod",+ "model_3d": "f280041cpzs-hero.glb",+ "model_3d_plain": "f280041cpzs.glb",+ "model_3d_step": "f280041cpzs-etched.step",+ "model_3d_step_plain": "f280041cpzs.step",+ "lbr": "f280041cpzs.lbr"+ },+ "distributor_links": {+ "lcsc": "C1342991",+ "digikey": "F280041CPZS-ND",+ "mouser": "595-F280041CPZS"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:52:38Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "F280041CPZS-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-F280041CPZS",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 on the 3.3 V VDDIO domain, with alternate functions including SCIA_RX, EPWM7_A, SD1_D3, SPIB_CLK and ERRORSTS."+ },+ {+ "number": "2",+ "name": "XRSn",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output (open-drain with internal pull-up); a 2.2 kΩ to 10 kΩ resistor to VDDIO is required, and any noise filter capacitor to VSS must be 100 nF or less."+ },+ {+ "number": "3",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground; all VSS pins must be connected to board ground."+ },+ {+ "number": "6",+ "name": "A6/PGA5_OF",+ "type": "input",+ "description": "ADC-A analog input 6, also the optional PGA-5 output filter pin; analog inputs must stay below VDDA + 0.3 V during operation."+ },+ {+ "number": "7",+ "name": "B2/C6/PGA3_OF",+ "type": "input",+ "description": "ADC-B analog input 2 (also ADC-C input 6) and optional PGA-3 output filter pin; analog inputs must stay below VDDA + 0.3 V."+ },+ {+ "number": "8",+ "name": "B3/VDAC",+ "type": "input",+ "description": "ADC-B analog input 3 and optional external reference for the on-chip DACs; a 100 pF capacitor to VSSA is always present, and at least 1 µF is required if VDAC is used as DAC reference."+ },+ {+ "number": "9",+ "name": "A2/B6/PGA1_OF",+ "type": "input",+ "description": "ADC-A analog input 2 (also ADC-B input 6) and optional PGA-1 output filter pin."+ },+ {+ "number": "10",+ "name": "A3",+ "type": "input",+ "description": "ADC-A analog input 3, also routed to CMPSS-1 comparator inputs."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "3.3 V analog supply; place a minimum 2.2 µF decoupling capacitor to VSSA on each VDDA pin."+ },+ {+ "number": "12",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground for the ADC, PGA, DAC and comparator circuits."+ },+ {+ "number": "13",+ "name": "PGA5_GND",+ "type": "power_in",+ "description": "PGA-5 Kelvin ground reference; should be bound to VSSA if the PGA is unused."+ },+ {+ "number": "14",+ "name": "PGA1_GND",+ "type": "power_in",+ "description": "PGA-1 Kelvin ground reference; should be bound to VSSA if the PGA is unused."+ },+ {+ "number": "15",+ "name": "PGA3_GND",+ "type": "power_in",+ "description": "PGA-3 Kelvin ground reference; should be bound to VSSA if the PGA is unused."+ },+ {+ "number": "16",+ "name": "PGA5_IN",+ "type": "input",+ "description": "PGA-5 non-inverting input, amplified with programmable gain of 3, 6, 12 or 24."+ },+ {+ "number": "17",+ "name": "C4",+ "type": "input",+ "description": "ADC-C analog input 4, also routed to CMPSS-5 comparator inputs."+ },+ {+ "number": "18",+ "name": "PGA1_IN",+ "type": "input",+ "description": "PGA-1 input with programmable gain of 3, 6, 12 or 24."+ },+ {+ "number": "19",+ "name": "C0",+ "type": "input",+ "description": "ADC-C analog input 0, also routed to CMPSS-1 comparator inputs."+ },+ {+ "number": "20",+ "name": "PGA3_IN",+ "type": "input",+ "description": "PGA-3 input with programmable gain of 3, 6, 12 or 24."+ },+ {+ "number": "21",+ "name": "C2",+ "type": "input",+ "description": "ADC-C analog input 2, also routed to CMPSS-3 comparator inputs."+ },+ {+ "number": "22",+ "name": "A1/DACB_OUT",+ "type": "input",+ "description": "ADC-A analog input 1; alternate function is the buffered 12-bit DAC-B output."+ },+ {+ "number": "23",+ "name": "A0/B15/C15/DACA_OUT",+ "type": "input",+ "description": "ADC-A analog input 0 (also ADC-B 15 and ADC-C 15); alternate function is the buffered 12-bit DAC-A output."+ },+ {+ "number": "24",+ "name": "VREFHIB/VREFHIC",+ "type": "bidirectional",+ "description": "ADC-B and ADC-C high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between this pin and VREFLO and no external loading."+ },+ {+ "number": "25",+ "name": "VREFHIA",+ "type": "bidirectional",+ "description": "ADC-A high reference; driven externally in external-reference mode or by the device in internal-reference mode, with at least 2.2 µF placed between this pin and VREFLOA and no external loading."+ },+ {+ "number": "26",+ "name": "VREFLOB/VREFLOC",+ "type": "input",+ "description": "ADC-B and ADC-C low reference, bound to VSSA in typical use."+ },+ {+ "number": "27",+ "name": "VREFLOA",+ "type": "input",+ "description": "ADC-A low reference, bound to VSSA in typical use."+ },+ {+ "number": "28",+ "name": "C5/PGA6_IN",+ "type": "input",+ "description": "ADC-C analog input 5; alternate function is the PGA-6 input, and it is also routed to CMPSS-6 comparator inputs."+ },+ {+ "number": "29",+ "name": "C1",+ "type": "input",+ "description": "ADC-C analog input 1, also routed to CMPSS-2 comparator inputs."+ },+ {+ "number": "30",+ "name": "PGA2_IN",+ "type": "input",+ "description": "PGA-2 input with programmable gain of 3, 6, 12 or 24."+ },+ {+ "number": "31",+ "name": "C3/PGA4_IN",+ "type": "input",+ "description": "ADC-C analog input 3; alternate function is the PGA-4 input, and it is also routed to CMPSS-4 comparator inputs."+ },+ {+ "number": "32",+ "name": "PGA2_GND,PGA4_GND,PGA6_GND",+ "type": "power_in",+ "description": "Shared PGA ground references for PGA-2, PGA-4 and PGA-6; bound to VSSA when those PGAs are unused."+ },+ {+ "number": "33",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground for the ADC, PGA, DAC and comparator circuits."+ },+ {+ "number": "34",+ "name": "VDDA",+ "type": "power_in",+ "description": "3.3 V analog supply; place a minimum 2.2 µF decoupling capacitor to VSSA on each VDDA pin."+ },+ {+ "number": "35",+ "name": "A5",+ "type": "input",+ "description": "ADC-A analog input 5, also routed to CMPSS-2 comparator inputs."+ },+ {+ "number": "36",+ "name": "A4/B8/PGA2_OF",+ "type": "input",+ "description": "ADC-A analog input 4 (also ADC-B input 8) and optional PGA-2 output filter pin."+ },+ {+ "number": "37",+ "name": "A8/PGA6_OF",+ "type": "input",+ "description": "ADC-A analog input 8 and optional PGA-6 output filter pin."+ },+ {+ "number": "38",+ "name": "A9",+ "type": "input",+ "description": "ADC-A analog input 9, also routed to CMPSS-6 comparator inputs."+ },+ {+ "number": "39",+ "name": "B4/C8/PGA4_OF",+ "type": "input",+ "description": "ADC-B analog input 4 (also ADC-C input 8) and optional PGA-4 output filter pin."+ },+ {+ "number": "40",+ "name": "A10/B1/C10/PGA7_OF",+ "type": "input",+ "description": "ADC-A analog input 10 (also ADC-B input 1 and ADC-C input 10) and optional PGA-7 output filter pin."+ },+ {+ "number": "41",+ "name": "B0",+ "type": "input",+ "description": "ADC-B analog input 0, also routed to CMPSS-7 comparator inputs."+ },+ {+ "number": "42",+ "name": "PGA7_GND",+ "type": "power_in",+ "description": "PGA-7 Kelvin ground reference; should be bound to VSSA if the PGA is unused."+ },+ {+ "number": "43",+ "name": "PGA7_IN",+ "type": "input",+ "description": "PGA-7 input with programmable gain of 3, 6, 12 or 24."+ },+ {+ "number": "44",+ "name": "C14",+ "type": "input",+ "description": "ADC-C analog input 14, also routed to CMPSS-7 comparator inputs."+ },+ {+ "number": "45",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground; all VSS pins must be connected to board ground."+ },+ {+ "number": "46",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used."+ },+ {+ "number": "47",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "48",+ "name": "FLT2",+ "type": "unconnected",+ "description": "Flash test pin 2, reserved by TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more)."+ },+ {+ "number": "49",+ "name": "FLT1",+ "type": "unconnected",+ "description": "Flash test pin 1, reserved by TI; must be left unconnected (or tied to VSS through 4.7 kΩ or more)."+ },+ {+ "number": "50",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O 13 with alternate functions including EPWM7_B, CANB_RX, EQEP1_INDEX, SCIB_RX, PMBUSA_ALERT (open-drain) and FSIRXA_CLK."+ },+ {+ "number": "51",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with alternate functions including EPWM7_A, CANB_TX, EQEP1_STROBE, SCIB_TX, PMBUSA_CTL and FSIRXA_D0."+ },+ {+ "number": "52",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O 11 with alternate functions including EPWM6_B, SCIB_RX, OUTPUTXBAR7, EQEP1_B, SPIA_STE and FSIRXA_D1."+ },+ {+ "number": "53",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with alternate functions including I2CA_SCL (open-drain), SPIB_STE, OUTPUTXBAR4, LINA_RX, SD1_C3, FSIRXA_CLK and CANA_RX."+ },+ {+ "number": "54",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 with alternate functions including SPIA_SIMO, CANB_TX, EPWM5_A, SCIA_TX, SD1_D1 and XCLKOUT."+ },+ {+ "number": "55",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 with alternate functions including SPIA_SOMI, CANB_RX, EPWM5_B, SCIA_RX, SD1_C1 and PMBUSA_SDA (open-drain)."+ },+ {+ "number": "56",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose I/O 24 with alternate functions including OUTPUTXBAR1, EQEP2_A, EPWM8_A, SPIB_SIMO, SD1_D1, SCIA_TX and ERRORSTS (active-low error status output)."+ },+ {+ "number": "57",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose I/O 25 with alternate functions including OUTPUTXBAR2, EQEP2_B, SPIB_SOMI, SD1_C1, FSITXA_D1, PMBUSA_SDA (open-drain) and SCIA_RX."+ },+ {+ "number": "58",+ "name": "GPIO26",+ "type": "bidirectional",+ "description": "General-purpose I/O 26 with alternate functions including OUTPUTXBAR3, EQEP2_INDEX, SPIB_CLK, SD1_D2, FSITXA_D0, PMBUSA_CTL and I2CA_SDA (open-drain)."+ },+ {+ "number": "59",+ "name": "GPIO27",+ "type": "bidirectional",+ "description": "General-purpose I/O 27 with alternate functions including OUTPUTXBAR4, EQEP2_STROBE, SPIB_STE, SD1_C2, FSITXA_CLK, PMBUSA_ALERT (open-drain) and I2CA_SCL (open-drain)."+ },+ {+ "number": "60",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input with internal pull-up."+ },+ {+ "number": "61",+ "name": "GPIO37/TDO",+ "type": "tri_state",+ "description": "JTAG test data output (default function) that is tri-stated when no JTAG activity is present; an internal or external pull-up is required to avoid a floating input when used as GPIO37."+ },+ {+ "number": "62",+ "name": "TMS",+ "type": "bidirectional",+ "description": "JTAG test mode select with internal pull-up; an external 2.2 kΩ pull-up to VDDIO is recommended on the board to hold JTAG in reset during normal operation."+ },+ {+ "number": "63",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "JTAG test data input (default function); internal pull-up is disabled by default, so an internal pull-up must be enabled or an external pull-up added when used as TDI."+ },+ {+ "number": "64",+ "name": "GPIO32",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with alternate functions including I2CA_SDA (open-drain), SPIB_CLK, EPWM8_B, LINA_TX, SD1_D3, FSIRXA_D0 and CANA_TX."+ },+ {+ "number": "65",+ "name": "GPIO56",+ "type": "bidirectional",+ "description": "General-purpose I/O 56 with alternate functions including SPIA_CLK, EQEP2_STROBE, SCIB_TX, SD1_D3, SPIB_SIMO and EQEP1_A."+ },+ {+ "number": "66",+ "name": "GPIO57",+ "type": "bidirectional",+ "description": "General-purpose I/O 57 with alternate functions including SPIA_STE, EQEP2_INDEX, SCIB_RX, SD1_C3, SPIB_SOMI and EQEP1_B."+ },+ {+ "number": "67",+ "name": "GPIO58",+ "type": "bidirectional",+ "description": "General-purpose I/O 58 with alternate functions including OUTPUTXBAR1, SPIB_CLK, SD1_D4, LINA_TX, CANB_TX and EQEP1_STROBE."+ },+ {+ "number": "68",+ "name": "GPIO18_X2",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 or crystal oscillator output X2; GPIO18 is usable only when the system is clocked by INTOSC and X1 has an external pull-down (recommended 1 kΩ)."+ },+ {+ "number": "69",+ "name": "X1",+ "type": "bidirectional",+ "description": "Crystal oscillator input or single-ended 3.3 V clock input; device software must configure this pin before enabling the crystal oscillator."+ },+ {+ "number": "70",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "71",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used."+ },+ {+ "number": "72",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground; all VSS pins must be connected to board ground."+ },+ {+ "number": "73",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal regulator enable with internal pull-down: tie to VSS to enable the internal VREG (and DC/DC), or tie to VDDIO to use an external VDD supply."+ },+ {+ "number": "74",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O 8 with alternate functions including EPWM5_A, CANB_TX, ADCSOCAO, EQEP1_STROBE, SCIA_TX, SPIA_SIMO, I2CA_SCL (open-drain) and FSITXA_D1."+ },+ {+ "number": "75",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with alternate functions including EPWM3_A, OUTPUTXBAR3, CANA_TX and FSIRXA_CLK."+ },+ {+ "number": "76",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with alternate functions including EPWM2_B, OUTPUTXBAR2, PMBUSA_SCL (open-drain), SPIA_CLK, SCIA_RX and FSIRXA_D0."+ },+ {+ "number": "77",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with alternate functions including EPWM2_A, OUTPUTXBAR1, PMBUSA_SDA (open-drain), SCIA_TX and FSIRXA_D1."+ },+ {+ "number": "78",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with alternate functions EPWM1_B and I2CA_SCL (open-drain)."+ },+ {+ "number": "79",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with alternate functions EPWM1_A and I2CA_SDA (open-drain)."+ },+ {+ "number": "80",+ "name": "VDDIO_SW",+ "type": "power_in",+ "description": "3.3 V supply for the internal DC/DC regulator; must be connected to VDDIO, with a 20 µF bulk input capacitor when the DC/DC is used."+ },+ {+ "number": "81",+ "name": "GPIO23_VSW",+ "type": "bidirectional",+ "description": "General-purpose I/O 23 or DC/DC switch output VSW (when DCDCEN = 1); the pin has about 100 pF internal capacitance, so TI recommends an alternate GPIO for fast-switching use."+ },+ {+ "number": "82",+ "name": "VSS_SW",+ "type": "power_in",+ "description": "Internal DC/DC regulator ground; must always be connected to VSS."+ },+ {+ "number": "83",+ "name": "GPIO22_VFBSW",+ "type": "bidirectional",+ "description": "General-purpose I/O 22 or DC/DC feedback VFBSW; when the internal DC/DC is used, connect this pin to the node where L(VSW) connects to the VDD rail as close to the device as possible."+ },+ {+ "number": "84",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with alternate functions including EPWM4_B, OUTPUTXBAR5, EQEP1_B, CANB_RX, SPIB_SIMO and FSITXA_CLK."+ },+ {+ "number": "85",+ "name": "GPIO40",+ "type": "bidirectional",+ "description": "General-purpose I/O 40 with alternate functions including PMBUSA_SDA (open-drain), FSIRXA_D0, SCIB_TX and EQEP1_A."+ },+ {+ "number": "86",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground; all VSS pins must be connected to board ground."+ },+ {+ "number": "87",+ "name": "VDD",+ "type": "power_in",+ "description": "1.2 V digital logic supply; total VDD decoupling of about 20 µF minimum is recommended near the VDD pins when the internal regulator is not used."+ },+ {+ "number": "88",+ "name": "VDDIO",+ "type": "power_in",+ "description": "3.3 V digital I/O supply; place a minimum 0.1 µF decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "89",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with alternate functions including EPWM3_B, OUTPUTXBAR3, CANA_RX, SPIA_STE and FSITXA_D1."+ },+ {+ "number": "90",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O 9 with alternate functions including EPWM5_B, SCIB_TX, OUTPUTXBAR6, EQEP1_INDEX, SCIA_RX, SPIA_CLK and FSITXA_D0."+ },+ {+ "number": "91",+ "name": "GPIO39",+ "type": "bidirectional",+ "description": "General-purpose I/O 39 with alternate functions CANB_RX and FSIRXA_CLK."+ },+ {+ "number": "92",+ "name": "GPIO59",+ "type": "bidirectional",+ "description": "General-purpose I/O 59 with alternate functions including OUTPUTXBAR2, SPIB_STE, SD1_C4, LINA_RX, CANB_RX and EQEP1_INDEX."+ },+ {+ "number": "93",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O 10 with alternate functions including EPWM6_A, CANB_RX, ADCSOCBO, EQEP1_A, SCIB_TX, SPIA_SOMI, I2CA_SDA (open-drain) and FSITXA_CLK."+ },+ {+ "number": "94",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 with alternate functions OUTPUTXBAR1 and PMBUSA_SDA (open-drain)."+ },+ {+ "number": "95",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "General-purpose I/O 15 with alternate functions including EPWM8_B, SCIB_RX, OUTPUTXBAR4, PMBUSA_SCL (open-drain), SPIB_STE and EQEP2_B."+ },+ {+ "number": "96",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O 14 with alternate functions including EPWM8_A, SCIB_TX, OUTPUTXBAR3, PMBUSA_SDA (open-drain), SPIB_CLK and EQEP2_A."+ },+ {+ "number": "97",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with alternate functions including EPWM4_A, OUTPUTXBAR4, SYNCOUT, EQEP1_A, CANB_TX, SPIB_SOMI and FSITXA_D0."+ },+ {+ "number": "98",+ "name": "GPIO30",+ "type": "bidirectional",+ "description": "General-purpose I/O 30 with alternate functions including CANA_RX, SPIB_SIMO, OUTPUTXBAR7, EQEP1_STROBE and SD1_D4."+ },+ {+ "number": "99",+ "name": "GPIO31",+ "type": "bidirectional",+ "description": "General-purpose I/O 31 with alternate functions including CANA_TX, SPIB_SOMI, OUTPUTXBAR8, EQEP1_INDEX, SD1_C4 and FSIRXA_D1."+ },+ {+ "number": "100",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 with alternate functions including SCIA_TX, EPWM7_B, OUTPUTXBAR6, EQEP1_B, SD1_C3, EQEP2_INDEX, LINA_RX, SPIB_STE and ERRORSTS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin list follows the 100 PZ column of Table 5-1 and the Figure 5-1 top-view (source page 10). All 10; Multi-function pins are typed by their primary function (ADC/analog input, reference, ground, or GPI; KiCad ERC has no open-drain type, so I/OD pins are mapped to bidirectional. XRSn (pin 2) is open-dra"+ ],+ "pages_sent": 146,+ "cost_usd": 1.1135,+ "at": "2026-10-07T21:52:05"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f280045",+ "pages": 277,+ "sha256": "867e7bb5ada6819c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "f280041cpzs.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "51720097260ffba41c3062f85f67623721102fa535901c47cb555a1f444feeb3",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "f280041cpzs-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "109994c15b5bc119cd08ae9094ccea836c3e83027985e4d7f55facd146e8875d",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}