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ETA9351Q4Y
Public Made by Adomby adom
etasolution Power Management - Specialized, QFN-24L-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+224−8@@ -1,13 +1,234 @@ {+ "schema_version": 1,+ "type": "component", "slug": "eta9351q4y",+ "title": "ETA9351Q4Y",+ "brief": "etasolution Power Management - Specialized, QFN-24L-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "etasolution Power Management - Specialized, QFN-24L-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "power management (pmic)", "eta9351q4y" ],+ "component": {+ "mpn": "ETA9351Q4Y",+ "manufacturer": "etasolution",+ "package": "QFN-24L-EP(4x4)",+ "pin_count": 25,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9460fa99f6f4a4d31e6dcb63333fc055.pdf",+ "parts": {+ "symbol": "eta9351q4y.kicad_sym",+ "footprint": "eta9351q4y.kicad_mod",+ "model_3d": "eta9351q4y.glb",+ "model_3d_step": "eta9351q4y.step",+ "lbr": "eta9351q4y.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "PGND3",+ "type": "power_in",+ "description": "Power ground for Channel 3 buck converter. Return path for the low-side NMOS switch current; route with a low-impedance connection to the input/output capacitor grounds."+ },+ {+ "number": "2",+ "name": "EN3",+ "type": "input",+ "description": "Enable input for Channel 3. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable. EN input current ~1 uA."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection. Per the PCB Layout Guide (page 7) this pin is used as a routing island; PGND2 (pin 11) is jumpered through the exposed pad to pin 3 to shorten the Channel 2 input capacitor return path."+ },+ {+ "number": "4",+ "name": "VIN2",+ "type": "power_in",+ "description": "Input supply voltage for Channel 2 (2.6 V to 5.5 V). Bypass with a 22 uF ceramic capacitor to PGND2 and a 10 nF capacitor to AGND2."+ },+ {+ "number": "5",+ "name": "SW2",+ "type": "output",+ "description": "Switching node for Channel 2. Connect a 1 uH inductor between SW2 and VOS2. Internally driven by the high-side PMOS and low-side NMOS power switches; SW current is internally limited (~4.5 A typ)."+ },+ {+ "number": "6",+ "name": "EN2",+ "type": "input",+ "description": "Enable input for Channel 2. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable."+ },+ {+ "number": "7",+ "name": "VIN1",+ "type": "power_in",+ "description": "Input supply voltage for Channel 1 (2.6 V to 5.5 V). Bypass with a 22 uF ceramic capacitor to PGND1 and a 10 nF capacitor to AGND1."+ },+ {+ "number": "8",+ "name": "EN1",+ "type": "input",+ "description": "Enable input for Channel 1. Drive high (>1.5 V) to enable the channel, low (<0.4 V) to disable."+ },+ {+ "number": "9",+ "name": "PGND1",+ "type": "power_in",+ "description": "Power ground for Channel 1 buck converter. Return path for the low-side NMOS switch current."+ },+ {+ "number": "10",+ "name": "SW1",+ "type": "output",+ "description": "Switching node for Channel 1. Connect a 1 uH inductor between SW1 and VOS1."+ },+ {+ "number": "11",+ "name": "PGND2",+ "type": "power_in",+ "description": "Power ground for Channel 2 buck converter. Per the PCB Layout Guide, route through the bottom exposed heat-dissipation pad over to pin 3 to shorten the Channel 2 input capacitor return path."+ },+ {+ "number": "12",+ "name": "FB1",+ "type": "input",+ "description": "Feedback input for Channel 1. Connect an external resistor divider from VOUT1 to FB1 and AGND1 to program the output between 0.45 V and VIN1. Regulation threshold is 0.45 V (0.441 V / 0.459 V min/max); input current ~0.01 uA."+ },+ {+ "number": "13",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog ground for Channel 1. Keep quiet by adding a 10 nF ceramic capacitor from VIN1 to AGND1."+ },+ {+ "number": "14",+ "name": "VOS1",+ "type": "input",+ "description": "Output voltage sense input for Channel 1. Connect directly to the Channel 1 regulated output node (post-inductor) for the internal on-time / voltage-mode control loop."+ },+ {+ "number": "15",+ "name": "FB2",+ "type": "input",+ "description": "Feedback input for Channel 2. Connect an external resistor divider from VOUT2 to FB2 and AGND2 to program the output between 0.45 V and VIN2."+ },+ {+ "number": "16",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for Channel 2. Add a 10 nF ceramic capacitor from VIN2 to AGND2 to keep this reference quiet."+ },+ {+ "number": "17",+ "name": "VOS2",+ "type": "input",+ "description": "Output voltage sense input for Channel 2. Connect directly to the Channel 2 regulated output node."+ },+ {+ "number": "18",+ "name": "FB3",+ "type": "input",+ "description": "Feedback input for Channel 3. Connect an external resistor divider from VOUT3 to FB3 and AGND3 to program the output between 0.45 V and VIN3."+ },+ {+ "number": "19",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for Channel 3. Add a 10 nF ceramic capacitor from VIN3 to AGND3 to keep this reference quiet."+ },+ {+ "number": "20",+ "name": "VOS3",+ "type": "input",+ "description": "Output voltage sense input for Channel 3. Connect directly to the Channel 3 regulated output node."+ },+ {+ "number": "21",+ "name": "PG3",+ "type": "output",+ "description": "Power-Good open-drain output for Channel 3. High-impedance when VOUT3 is within regulation (rising threshold 90% of nominal, 2.5% hysteresis); pulls low (VOL <=0.4 V at 1 mA sink) when VOUT3 is below its nominal value. The external pull-up must not exceed VIN3."+ },+ {+ "number": "22",+ "name": "SW3",+ "type": "output",+ "description": "Switching node for Channel 3. Connect a 1 uH inductor between SW3 and VOS3."+ },+ {+ "number": "23",+ "name": "PVIN3",+ "type": "power_in",+ "description": "Power input supply for Channel 3 (2.6 V to 5.5 V). Feeds the Channel 3 high-side PMOS power switch. Bypass with a 22 uF ceramic capacitor to PGND3 and a 10 nF capacitor to AGND3; tie together with AVIN3."+ },+ {+ "number": "24",+ "name": "AVIN3",+ "type": "power_in",+ "description": "Analog input supply for Channel 3 (2.6 V to 5.5 V). Feeds the Channel 3 analog/control circuitry. Bypass with a 22 uF ceramic capacitor to PGND3 and a 10 nF capacitor to AGND3; typically tied to PVIN3."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Exposed thermal pad on the bottom of the QFN-24 package. Must be soldered to the PCB ground plane for electrical ground and thermal dissipation (theta-JA = 30 degC/W). Also serves as a routing plane between PGND2 (pin 11) and pin 3 per the PCB Layout Guide."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9460fa99f6f4a4d31e6dcb63333fc055.pdf",+ "pages": 9,+ "sha256": "b31a7ee0be5fc574",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "etasolution",+ "Package": "QFN-24L-EP(4x4)",+ "Category": "Power Management (PMIC)",+ "Pins": "25"+ }+ },+ "variants": [+ {+ "mpn": "ETA9351Q4Y",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "eta9351q4y"+ ],+ "discovery_pitch": "ETA9351Q4Y (etasolution) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +246,5 @@ "docs/eta9351q4y-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }